Revision History
A
Revision History
99
Table 62: Revision History
Revision
Date
Comments
E
December 2, 2008
Revision
1. In Figure 1, 88F6180 Pin Logic Diagram, on page 16, changed the GE_TXCLKOUT pin to input/output and added a
note under the figure, stating that the pin is an input when used the MII/MMII Transmit Clock.
2. In Table 3, Power Pin Assignments, on page 19, revised the description of the VDD_GE pin.
3. In Table 4, Miscellaneous Pin Assignments, on page 20, revised the description of the ISET pin.
4. In Table 6, PCI Express Interface Pin Assignments, on page 23, revised the description of the PEX_CLK_P/N pins to
state that they can be configured as input or output according to the reset strap.
5. In Table 7, Gigabit Ethernet Port Interface Pin Assignments, on page 24, added a description of the MII/MMII Transmit
Clock to the description of the GE_TXCLKOUT pin.
6. In Table 11, RTC Interface Pin Assignments, on page 29, changed the type for RTC_XOUT to analog.
2
7. In the description of signal AU_SPDFRMCLK in Table 16, Audio (S/PDIF / I S) Interface Signal Assignment, on
page 34, added a reference to the new AU_SPDFRMCLK information in the Reference Clock AC Timing
Specifications table.
8. In Table 21, Unused Interface Strapping, on page 39, revise the description for configuring the PCI Express clock
signals.
9. At the end of Gigabit Ethernet (GbE) Pins Multiplexing on MPP, added a note stating that all relevant Gigabit Ethernet
signals must be implemented.
10. In Table 32, Recommended Operating Conditions, on page 61, for parameter RTC_AVDD Analog supply for RTC in
Battery Back-up mode, revised the values for the minimum to 1.3V from 1.4V and for the maximum to 1.7V from 1.6V.
11. In Table 33, Thermal Power Dissipation, on page 63, for the eFuse during Burning mode parameter added a note:
The eFuse burn is done once, and there should be no thermal effect, after it has been burned.
12. In Table 40, Reference Clock AC Timing Specifications, on page 69:
•
•
•
Revised the names of the Ethernet transmit symbols to F
Added the S/PDIF Recovered Master Clock.
For the PTP reference clock, revised the values for the Frequency, Duty Cycle, and Pk-Pk jitter parameters.
, DC
, and SR
.
GE_TXCLK_OUT
GE_TXCLK_OUT
GE_TXCLK_OUT
D
October 5, 2008 Revision
1. In Table 6, PCI Express Interface Pin Assignments, on page 23, revised the note in the description of the
PEX_CLK_P/N pins.
2. In Table 20, Internal Pull-up and Pull-down Pins, on page 38, revised the pin number for MRn from G04 to G03.
3. In Table 21, Unused Interface Strapping, on page 39, added the eFuse strapping.
4. Revised the attached excel pin map and pin list. See the revision history in the excel file for a list of the pin changes.
5. In Section 6.1.1, Power-Up Sequence Requirements, on page 48 and Section 6.1.2, Power-Down Sequence
Requirements, on page 49, added a power up/down requirements for when VHV is in eFuse Burning mode.
6. In Table 32, Recommended Operating Conditions, on page 61:
•
For VHV, revised the two parameters to VHV (during eFuse Burning mode) and VHV (during eFuse Reading mode)
and added notes in the comments column for both VHV voltages.
•
•
For VDD_M, PEX_AVDD, and USB_AVDD, revised the comments column.
for RTC_AVDD, revised the values for minimum to 1.4V from 1.3V and for maximum to 1.6V from 1.7V.
7. In Table 33, Thermal Power Dissipation, on page 63, revised the row for the SDRAM and added a row for the eFuse.
Copyright © 2008 Marvell
Doc. No. MV-S104988-U0 Rev. E
Page 105
December 2, 2008, Preliminary
Document Classification: Proprietary Information
MARVELL [ MARVELL TECHNOLOGY GROUP LTD. ]
