88F6180
Hardware Specifications
FEATURES
The 88F6180 includes:
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High-performance CPU core, running at up to
800 MHz, with integrated, four-way, set-associative
L1 16-KB I-cache/16-KB D-cache and unified,
256-KB, four-way, set-associative L2 cache
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High-bandwidth dual-port DDR2 memory interface
(16-bit DDR2 SDRAM @ up to400 MHz data rate)
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PCI Express (x1) port with integrated PHY
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Gigabit Ethernet (10/100/1000 Mbps) MAC
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USB 2.0 port with integrated PHY
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Security Cryptographic engine
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S/PDIF (Sony/Philips Digital Interconnect Format) /
I
2
S (Integrated Interchip Sound) Audio in/out
interface
SD/SDIO/MMC interface
Two XOR engines, each containing two XOR/DMA
channels (a total of four XOR/DMA channels)
SPI port with SPI flash boot support
8-bit NAND flash interface with boot support
Two 16550 compatible UART interfaces
TWSI port
30 multi-purpose pins
Internal Real Time Clock (RTC)
Interrupt controller
Timers
128-bit eFuse (one-time programmable memory)
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Supports two DRAM chip selects
Supports all DDR devices densities up to 1 Gb
Supports up to 16 open pages (page per bank)
Up to 512 MB total address space
Supports on-board DDR designs (no DIMM
support)
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Supports 2T mode, to enable high-frequency
operation under heavy load configuration
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Supports DRAM bank interleaving
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Supports up to a 128-byte burst per single memory
access
PCI Express interface (x1)
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PCI Express Base 1.1 compatible
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Integrated low-power SERDES PHY, based on
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Sheeva
™
CPU core
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Up to 800 MHz
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32-bit and 16-bit RISC architecture
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Compliant with v5TE architecture, as published in
the
ARM Architect Reference Manual,
Second
Edition
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Includes MMU to support virtual memory features
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256-KB, four-way, set-associative L2 unified cache
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16-KB, four-way, set-associative I-cache
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16-KB, four-way, set-associative D-cache
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64-bit internal data bus
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Branch Prediction Unit
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Supports JTAG/ARM ICE
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Supports both Big and Little Endian modes
DDR2 SDRAM controller
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16-bit interface
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Up to 200 MHz clock frequency (400 MHz data
rate)
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DDR SDRAM with a clock ratio of 1:N and 2:N
between the DDR SDRAM and the CPU core,
respectively
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SSTL 1.8V I/Os
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Auto calibration of I/Os output impedance
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proven Marvell
®
SERDES technology
Serves as a Root Complex or an Endpoint port
x1 link width
2.5 Gbps data rate
Lane polarity reversal support
Maximum payload size of 128 bytes
Single Virtual Channel (VC-0)
Replay buffer support
Extended PCI Express configuration space
Advanced Error Reporting (AER) support
Power management: L0s and software L1 support
Interrupt emulation message support
Error message support
PCI Express master specific features
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Single outstanding read transaction
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Maximum read request of up to 128 bytes
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Maximum write request of up to 128 bytes
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Up to four outstanding read transactions in
Endpoint mode
PCI Express target specific features
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Supports up to eight read request transactions
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Maximum read request size of 4 KB
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Maximum write request of 128 bytes
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Supports PCI Express access to all of the
controller’s internal registers
Integrated GbE (10/100/1000) MAC port
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Supports 10/100/1000 Mbps
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Dedicated DMA for data movement between
memory and port
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Priority queuing on receive based on Destination
Address (DA), VLAN Tag, and IP TOS
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Layer 2/3/4 frame encapsulation detection
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TCP/IP checksum on receive and transmit
Doc. No. MV-S104988-U0 Rev. E
Page 4
Document Classification: Proprietary Information
Copyright © 2008 Marvell
December 2, 2008, Preliminary
MARVELL [ MARVELL TECHNOLOGY GROUP LTD. ]
