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88X2242 参数 Datasheet PDF下载

88X2242图片预览
型号: 88X2242
PDF下载: 下载PDF文件 查看货源
内容描述: 集成的双端口和四端口多功能高速以太网收发器与MACSec的电子色散补偿技术 [Integrated Dual-port and Quad-port Multi-speed Ethernet Transceiver with MACSec and Electronic Dispersion Compensation Technology]
分类和应用: 电子以太网
文件页数/大小: 2 页 / 517 K
品牌: MARVELL [ MARVELL TECHNOLOGY GROUP LTD. ]
 浏览型号88X2242的Datasheet PDF文件第2页  
Marvell Alaska X 88X2222/M and 88X2242/M
Integrated Dual-port and Quad-port Multi-speed Ethernet Transceiver
with MACSec and Electronic Dispersion Compensation Technology
PRODUCT OVERVIEW
The Marvell® Alaska® X 88X2222/M and 88X2242/M transceiver family is a fully integrated single-chip solution providing end-to-
end data transmission over fiber-optic networks as well as Twinax copper links. It offers 2- or 4-port devices that perform all
physical layer functions associated with 10GBASE-R, 2000BASE-X, 1000BASE-X and 10GBASE-W. In addition, the device
supports one port of 10GBASE-X4, 40GBASE-R4 and 10GBASE-X2.
The electronic dispersion compensation (EDC) engine delivers high-speed bidirectional point-to-point full duplex data transmis-
sion at 10.3 Gbps per port over a variety of media. The performance of the engine can be reduced to save power in fiber-optic
applications that do not require EDC.
The host-side interface supports two or four ports of 10GBASE-R, 10GBASE-X2, 2000BASE-X or 1000BASE-X with two ports
of 40GBASE-R4 or 10GBASE-X4, and one port of 40GBASE-R8. Any port from the host side can be attached to any port on
the line side as long as the speeds match. The device outputs a recovered clock for use in synchronous Ethernet applications.
The 88X2242M supports the Marvell LinkCrypt® feature, which is based on the IEEE802.1ae MACSec protocol. The 88X2242M
device also supports the features above those required by the IEEE802.1ae MACSec protocol. These include the ability to select
and filter uncontrolled port traffic; support of packet redirection by addition of a new MAC DA, SA and Ethertype; support of
latency minimization for flow control packets; and support for diagnostics, MACSec header retention and additional statistics
counters. The device also supports the ability to select a secure channel by means other than the SCI, FIPS compliance testing,
adaptive rate control to compensate for packet expansion and Ethertype matching for the uncontrolled path.
PART NUMBER
88X2222
88X2222M
88X2242
88X2242M
DESCRIPTION
2-port
2-port with MACSec
4-port
4-port with MACSec
Quad XFI / Quad RXAUI / Dual XAUI
Dual 40GBASE-R4 / Single 40GBASE-R8
Host Interface
MACSec (88X2242M Only)
Config.
JTAG
SynchE
EDC
SR / LR / DAC / LRM – 10G / 40G
Frame to Reg.
MDIO
LED
I2C
Quad SFP+ / Single QSFP+
Fig 1. 88X2242/M System Block Diagram