MV78100
Hardware Specifications
9.6.11
Time Division Multiplexing (TDM) Interface AC Timing
9.6.11.1
TDM Interface AC Timing Table
Table 50: TDM Interface AC Timing Table
16.384 MHz
Description
PCLK cycle time
Symbol
1/tC
Min
0.256
0.4
-
Max
Units
MHz
tC
Notes
1, 3
16.384
PCLK duty cycle
tDTY
tR/tF
tD
0.6
3.0
10.0
-
1
PCLK rise/fall time
ns
1, 2, 8
1, 4, 6
5, 7
DTX and FSYNC valid after PCLK rising edge
DRX and FSYNC setup time relative to PCLK falling edge
DRX and FSYNC hold time relative to PCLK falling edge
0.0
5.0
5.0
ns
tSU
ns
tHD
-
ns
5, 7
Notes :
General comment: All values w ere measured from vddio/2 to vddio/2, unless otherw ise specified.
1. For all signals, the load is CL = 20 pF.
2. Rise and Fall times are referenced to the 20% and 80% levels of the w aveform.
3. PCLK can be configured to 0.256, 0.512, 0.768, 1.024, 1.536, 2.048, 4.096, 8.192, 16.384 MHz frequencies only.
4. This parameter is relevant to FSYNC signal in master-mode only.
5. This parameter is relevant to FSYNC signal in slave-mode only.
6. In negative-mode, the DTX signal is relative to PCLK falling edge.
7. In negative-mode, the DRX signal is relative to PCLK rising edge.
8. This parameter is relevant w hen the PCLK pin is output.
9.6.11.2
TDM Interface Test Circuit
Figure 38: TDM Interface Test Circuit
Test Point
CL
MV-S104552-U0 Rev. D
Page 102
Copyright © 2008 Marvell
Document Classification: Proprietary Information
December 6, 2008, Preliminary
MARVELL [ MARVELL TECHNOLOGY GROUP LTD. ]
