Electrical Specifications
9.6.5
Serial Management Interface (SMI) AC Timing
9.6.5.1
SMI Master Mode AC Timing Table
Table 35: SMI Master Mode AC Timing Table
Description
MDC clock frequency
Symbol
fCK
Min
Max
Units
MHz
tCK
ns
Notes
See note 2
2
-
MDC clock duty cycle
tDC
0.4
40.0
0.0
0.6
MDIO input setup time relative to MDC rise time
MDIO input hold time relative to MDC rise time
MDIO output valid before MDC rise time
MDIO output valid after MDC rise time
tSU
-
-
-
-
-
tHO
ns
-
tOVB
tOVA
15.0
15.0
ns
1
1
ns
Notes :
General comment: All timing values w ere measured from VIL(max) and VIH(min) levels, unless otherw ise specified.
General comment: tCK = 1/fCK.
1. For MDC signal, the load is CL = 390 pF, and for MDIO signal, the load is CL = 470 pF.
2. See "Reference Clocks" table for more details.
9.6.5.2
SMI Master Mode Test Circuit
Figure 16: MDIO Master Mode Test Circuit
VDDIO
Test Point
2 kilohm
MDIO
CL
Copyright © 2008 Marvell
MV-S104552-U0 Rev. D
Page 79
December 6, 2008, Preliminary
Document Classification: Proprietary Information
MARVELL [ MARVELL TECHNOLOGY GROUP LTD. ]
