DA6179.000
22 January, 2007
TYPICAL APPLICATION (Continued)
Both the AGC and DEC capacitors can be connected either to VDD or to VSS. To minimize leakage currents
during power down the AGC and DEC capacitors are best to be connected to VDD since in power down the
AGC and DEC pins go to VDD voltage potential. In this case the positive polarity pin of electrolyte capacitor
should be connected to VDD. If the capacitors are connected to VSS then the negative polarity pin of electrolyte
capacitor should be connected to VSS.
Note 3: Power Down / Fast Startup Control
Both power down and fast startup are controlled using the PDN pin. The device is in power down (turned off) if
PDN1 = PDN2 = VDD and in power up with other three PDN1 and PDN2 control bit combinations (see table 1 on
page 4). Fast startup is triggered automatically when moving from power down to power up. The VDD must have
been high before moving from power down to power up to guarantee proper operation of fast startup circuitry.
Additionally the device should have been kept in power down state at least 50ms before power up. This
guarantees that the AGC capacitor voltage has been completely pulled to VDD during power down. The startup
time without proper fast startup control can be several minutes. With fast startup it is shortened typically to few
seconds.
Note 4: Optional Control for AGC On/Hold
AON control pin has internal pull up which turns AGC circuit on all the time if AON pin is left unconnected.
Optionally AON control can be used to hold and release AGC circuit. Stepper motor drive of analog clock or
watch can produce disturbing amount of noise which can shift the input amplifier gain to unoptimal level. This
can be avoided by controlling AGC hold (AON=VSS) during stepper motor drive periods and releasing AGC
(AON=VDD) when motors are not driven. The AGC should be in hold only during disturbances and kept on other
time released since due to leakage the AGC can change slowly when in hold.
Note 5: Ferrite Antenna
The ferrite antenna converts the transmitted radio wave into a voltage signal. It has an important role in
determining receiver performance. Recommended antenna impedance at resonance is around 150 kΩ.
Low antenna impedance corresponds to low noise but often also to small signal amplitude. On the other hand
high antenna impedance corresponds to high noise but also large signal. The optimum performance where
signal-to-noise ratio is at maximum is achieved in between.
The antenna should have also some selectivity for rejecting near signal band disturbances. This is determined
by the antenna quality factor which should be approximately 100. Much higher quality factor antennas suffer from
extensive tuning accuracy requirements and possible tuning drifts by the temperature.
Antenna impedance can be calculated using equation 1 where f
0
, L, Q
ant
and C are resonance frequency, coil
inductance, antenna quality factor and antenna tuning capacitor respectively. Antenna quality factor Q
ant
is
defined by ratio of resonance frequency f
0
and antenna bandwidth B (equation 2).
R
antenna
=
2
π
⋅
f
0
⋅
L
⋅
Q
antenna
=
Q
antenna
=
f
0
B
Q
antenna
1
=
2
π
⋅
f
0
⋅
C
2
π
⋅
B
⋅
C
Equation 1.
Equation 2.
Table 5 below presents some antenna manufacturers for time signal application.
Table 5.
Antenna Manufacturers and Antenna Types in Alphaphetical Order for Time Signal Application
Manufacturer
Antenna Type
Dimensions
Web Link
HR Electronic GmbH
Sumida
60716 (60kHz)
60708 (77.5kHz)
ACL80A (40kHz)
ø 10 x 60 mm
ø 10 x 80 mm
http://www.hrelectronic.com/
www.sumida.co.jp/jeita/XJA021.pdf
8 (10)
MAS [ MICRO ANALOG SYSTEMS ]
