MAS6501BA1WA300 参数 Datasheet PDF下载

DA6501.001

27 October 2008

MAS6501 PAD LAYOUT

1740

µ

m

PI

TE2

GND

COMMON

TE1

SCL

Y-coordinate

-839

µm

-839

µm

-839

µm

-839

µm

-839

µm

-839

µm

839

µm

839

µm

839

µm

839

µm

839

µm

839

µm

NI

6501

MCLK

XCLR

EOC

VDD

Die dimensions 1740 µm x 2090 µm; round PAD

∅

80

µm

Note:

Because the substrate of the die is internally connected to GND, the die has to be placed over a GND

plate on PCB or left floating. Please make sure that GND is the first pad to be bonded. Pick-and-place and all

component assembly are recommended to be performed in ESD protected area.

Note:

Coordinates are pad center points where origin has been located in the center of the silicon die.

Pad Identification

Name

X-coordinate

-713

µm

-450

µm

-200

µm

-18

µm

318

µm

726

µm

-713

µm

-450

µm

-200

µm

-18

µm

318

µm

726

µm

End of Conversion

EOC

Power Supply

VDD

Master Clock

MCLK

Clear I2C, Stop Conversion

XCLR

Serial Bus Data Input/Output

SDA

Serial Bus Clock

SCL

Supply Ground

GND

Sensor Ground

COMMON

ADC Positive Input

PI

Test Pin 2

TE2

ADC Negative Input

NI

Test Pin 1

TE1

Note:

Test pins TE1 and TE2 must be left floating.

6501

SDA

2090

µ

m

10 (16)