DA9116.005
22 November, 2005
REGISTER DESCRIPTION
Register
Peak Detector Status
CR4
7
X
6
1
5
0
Address Byte
4
1
3
1
2
R/W
1
X
0
X
Data Byte
msb…lsb
Output code
00000000
00000001
00000010
00000011
Input code
11111111
11111110
11111101
•
•
00000010
00000001
00000000
Function
Peak Detector Reference
CR3
X
1
1
0
0
R/W
X
X
Left Channel Gain
CR2
X
1
1
0
1
R/W
X
X
Right Channel Gain
CR1
X
1
1
1
0
R/W
X
X
Test, CR5
Both Channel Gains
X
X
1
1
1
0
1
0
1
1
R/W
W
X
X
X
X
No overload
Right overload
Left overload
Both overload
DAC output
VREF(255)
VREF(254)
VREF(253)
•
•
VREF(2)
VREF(1)
VREF(0)
Note 1
Input code
Gain dB
11111111
+15.5
+15.0
11111110
+14.5
11111101
•
•
•
•
11100000
0.0
00000010
-111.0
00000001
-111.5
00000000
mute
Input code
Gain dB
11111111
+15.5
+15.0
11111110
11111101
+14.5
•
•
•
•
11100000
0.0
00000010
-111.0
00000001
-111.5
00000000
mute
Reserved
Write to both gain registers
Note 1.
Reference voltage is calculated from VREF(CODE)=(0.16+0.0133*CODE)*VDD
Address byte bits:
•
Bit 2 is read/write bit (1=read, 0=write).
•
X is don’t care, recommended high for low
power.
Data byte bits:
•
All registers get their default value 00Hex except
CR3 which gets FFHex during power-on reset.
•
Default value for all bits is zero (00hex).
5 (18)
MAS [ MICRO ANALOG SYSTEMS ]
