Simple, Efficient, 1-Cell Li+ Pulse Charger
from 4.2V, and/or a reverse-current-protection diode
can be added in line at the source.
If the input is shorted, the MAX1879 will not allow current
to flow from BATT back through IN to the source.
However, the body diode inherent in the enhancement-
mode FET would still allow the cell to discharge rapidly.
To prevent this, add a power Schottky diode between
the source and IN as in Figure 4.
Therefore, the additional system error is simply the R
ADJ
tolerance multiplied by the percent change in the bat-
tery regulation voltage, or (1%)(2.4%) = 0.024%.
MAX1879
Selecting Minimum On-Time
The minimum pulse on-times can be selected by con-
necting TSEL as indicated in Table 2. A short pulse
time may be preferred to minimize voltage overshoot at
the battery and prevent pack overvoltage protection
circuitry from prematurely activating. A long minimum
on-time may be needed when using AC adapters with
high turn-on overshoot to allow charging current to set-
tle before the end of the pulse.
Adjusting the Battery Regulation Voltage
A typical Li+ cell should be charged at a constant cur-
rent until it reaches a voltage of about 4.2V, then
charged at this voltage until the current decays below a
predetermined level. The MAX1879 provides a simple
way to reduce this maximum target voltage with a sin-
gle resistor between ADJ and GND. Internally, ADJ
connects to a precision 1.4V reference through a 10kΩ
resistor. Leave ADJ open for a battery regulation volt-
age (V
BR
) of 4.2V; connect a 1% resistor from ADJ to
GND to form a voltage-divider for lower battery regula-
tion voltage (V
BR
′
)
.
Select the external value using:
R
ADJ
=
10k
Ω
V
BR
−
1
V
BR
′
Selecting External Components
Power Supply
One reason the MAX1879 Li+ cell-charging solution is
so compact and simple is that the charging current is
set by the external power source, not by the MAX1879
charging circuit. The PMOS FET in this application cir-
cuit is either on or off, allowing the source to be directly
connected to the cell or completely disconnected.
Therefore, it is very important to choose a power supply
Table 2. TSEL Minimum On-Time Settings
TSEL
CONNECTION
BATT
ADJ
GND
MINIMUM ON-TIME IN TOP-OFF
(ms)
34
69
137
A 1% tolerance resistor at ADJ degrades system accu-
racy by only a fraction of a percent. For example, an
R
ADJ
of 410kΩ ±1% reduces the battery regulation volt-
age by 2.4% (V
BR
′
= 4.1V from equation above, and
(V
BR
′
- V
BR
) / V
BR
= (4.1 - 4.2) / 4.2 = -2.4%).
CURRENT-LIMITED
WALL CUBE
(800mA, 6V max)
PMOS FET
FAIRCHILD FDC638P
-4.5A, -20V
0.07Ω AT V
GS
= -2.5V
CURRENT-LIMITED SCHOTTKY DIODE
30V, 1A
WALL CUBE
ZETEX ZHCS1000
(800mA, 6V max)
PMOS FET
FAIRCHILD FDC638P
-4.5A, -20V
0.07Ω AT V
GS
= -2.5V
GATE
GATE
IN
IN
MAX1879
TSEL*
ADJ
THERM
10kΩ
2.2µF
SINGLE
Li+
CELL
0.001µF
BATT
5mA
LED
CHG
CHG
0.001µF
R
ADJ
410kΩ
1%**
MAX1879
BATT
SINGLE
Li+
CELL
TSEL*
ADJ THERM
2.2µF
NTC THERMISTOR
FENWAL
140-103LAG-RBI
(10kΩ AT 25°C)
*SEE TABLE 2 FOR TSEL POSITION AND ASSOCIATED TIMER SETTINGS.
*SEE TABLE 2 FOR TSEL POSITION AND ASSOCIATED TIMER SETTINGS.
** R
ADJ
SETS BATTERY REGULATION VOLTAGE TO 4.10V; LEAVE OPEN
FOR 4.2V.
Figure 1. Simple Application Circuit
Figure 2. Application Circuit Including LED and Thermistor
9
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