Low-Cost, High-Frequency, Current-Mode PWM
Buck Controller
N1 operates as a duty-cycle control switch and has the
following ꢀajor losses: the channel conduction loss
ꢀended due to their low ESR and ESL at high frequency,
with relatively low cost. Choose a capacitor that exhibits
less than 10°C teꢀperature rise at the ꢀaxiꢀuꢀ operat-
ing RMS current for optiꢀuꢀ long-terꢀ reliability.
(P
), the voltage and current overlapping switching
N1CC
loss (P
), and the drive loss (P
).
N1SW
N1DR
Output Capacitor
The key selection paraꢀeters for the output capacitor
are the actual capacitance value, the equivalent series
resistance (ESR), the equivalent series inductance
(ESL), and the voltage-rating requireꢀents. These para-
ꢀeters affect the overall stability, output voltage ripple,
and transient response. The output ripple has three
coꢀponents: variations in the charge stored in the out-
put capacitor, the voltage drop across the capacitor’s
ESR, and the voltage drop across the ESL caused by
the current into and out of the capacitor:
V
2
OUT
P
=
× I
× R
USE R
AT T
DS(ON) J(MAX)
LOAD
N1CC
DS(ON)
(
)
V
IN
Q
+ Q
GD
GS
I
P
= V × I
IN LOAD
×
× f
S
N2SW
GATE
where I
is the average DH driver output current
GATE
capability deterꢀined by:
1
2
V
IN
I
≅
×
GATE
R
+ R
DH GATE
V
= V
+ V
+ V
RIPPLE
RIPPLE
(ESR)
RIPPLE(C) RIPPLE(ESL)
where R
is the high-side MOSFET driver’s on-resis-
DH
tance (3Ω ꢀax) and R
is the internal gate resis-
GATE
The output voltage ripple as a consequence of the ESR,
ESL, and output capacitance is:
tance of the MOSFET (~ 2Ω):
V
= I
× ESR
RIPPLE
(ESR)
P−P
R
GATE
P
= Q × V × f
×
N1DR
G
GS
S
I
P−P
R
+ R
DH
GATE
V
RIPPLE(C)
8×C
× f
OUT
S
where V
~ V . In addition to the losses above, allow
IN
GS
V
about 20% ꢀore for additional losses due to MOSFET
output capacitances and N2 body diode reverse recov-
ery charge dissipated in N1 that exists, but is not well
defined in the MOSFET data sheet. Refer to the MOS-
FET data sheet for the therꢀal-resistance specification
to calculate the PC board area needed to ꢀaintain the
desired ꢀaxiꢀuꢀ operating junction teꢀperature with
the above calculated power dissipations.
IN
V
ESL
RIPPLE(ESL) =
L
V
− V
OUT
V
IN
OUT
I
=
×
P−P
f
× L
V
IN
S
where I
is the peak-to-peak inductor current (see the
P-P
Determining the Inductor Value section). These equa-
tions are suitable for initial capacitor selection, but final
values should be chosen based on a prototype or eval-
uation circuit.
The ꢀiniꢀuꢀ load current ꢀust exceed the high-side
MOSFET’s ꢀaxiꢀuꢀ leakage current over teꢀperature
if fault conditions are expected.
As a general rule, a sꢀaller current ripple results in less
output voltage ripple. Since the inductor ripple current
is a factor of the inductor value and input voltage, the
output voltage ripple decreases with larger inductance,
and increases with higher input voltages. Ceraꢀic
capacitors are recoꢀꢀended for the MAX1953 due to
its 1MHz switching frequency. For the MAX1954/
MAX1957, using polyꢀer, tantaluꢀ, or aluꢀinuꢀ elec-
trolytic capacitors is recoꢀꢀended. The aluꢀinuꢀ
electrolytic capacitor is the least expensive; however, it
has higher ESR. To coꢀpensate for this, use a ceraꢀic
capacitor in parallel to reduce the switching ripple and
noise. For reliable and safe operation, ensure that the
capacitor’s voltage and ripple-current ratings exceed
the calculated values.
Input Capacitor
The input filter capacitor reduces peak currents drawn
froꢀ the power source and reduces noise and voltage
ripple on the input caused by the circuit’s switching.
The input capacitor ꢀust ꢀeet the ripple current
requireꢀent (I
) iꢀposed by the switching currents
RMS
defined by the following equation:
I
×
V
× V −V
(
)
LOAD
OUT
IN
OUT
I
=
RMS
V
IN
I
has a ꢀaxiꢀuꢀ value when the input voltage
RMS
equals twice the output voltage (V = 2 x V
), where
IN
OUT
I
= I
/2. Ceraꢀic capacitors are recoꢀ-
RMS(MAX)
LOAD
______________________________________________________________________________________ 17
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
