Microprocessor and Nonvolatile
Memory Supervisory Circuits
MAX792/MAX820
V
IN
MR
RESET
25µs MIN
12µs TYP
4 RESET IN/INT
3
V
CC
RESET
2
TO
µP
CE IN OV
CE OUT
5
15µs TYP
MAX792
LLIN/REFOUT
RESET
1
TO
µP
LOW LINE
10
TO
µP
NMI
Figure 2. Manual-Reset Timing Diagram
MANUAL RESET
9
*
OTHER
RESET
SOURCES
*
.
.
.
GND
12
MR
Figure 4a. Connection for Internal Threshold Mode
MAX792
MAX820
R1
V
IN
3
V
CC
RESET IN/INT
RESET
2
TO
µP
*
DIODES NOT REQUIRED ON OPEN-DRAIN OUTPUTS
Figure 3. Diode "OR" connections allow multiple reset sources
to connect to
MR
.
R2
MAX792
LLIN/REFOUT
RESET
1
TO
µP
Low-Line Output
In internal threshold mode, the low-line comparator
monitors V
CC
with a threshold voltage typically 120mV
above the reset threshold, and with 15mV of hysteresis.
For normal operation (V
CC
above the reset threshold),
LOWLINE
is pulled to V
CC
. Use
LOWLINE
to provide an NMI
to the µP, as described in the previous section, when
V
CC
begins to fall (Figure 4).
R3
LOW LINE
GND
12
R3 = 1.30V x V
CC MAX
V
LOW LINE
x I
MAX
R2 = 1.30V x V
CC MAX –
R3
V
RESET
x I
MAX
R1 = V
CC MAX
– (R2 + R3)
I
MAX
10
TO
µP
NMI
I
MAX
= THE MAXIMUM DESIRED CURRENT
THROUGH THE VOLTAGE DIVIDED.
Reset Function
The MAX792/MAX820 provide both RESET and
RESET
outputs. The RESET and
RESET
outputs ensure that the
µP powers up in a known state, and prevent code-exe-
cution errors during power-up, power-down, or
brownout conditions.
The reset function will be asserted during the following
conditions:
1) V
CC
less than the programmed reset threshold.
2)
MR
less than 1.30V typ.
3) Reset remains asserted for 200ms typ after V
CC
rises above the reset threshold or after
MR
has
exceeded 1.30V typ.
10
Figure 4b. Connection for External Threshold Programming Mode
When reset is asserted, all the internal counters are
reset, the watchdog output (WDO) and watchdog-pulse
output (WDPO) are set high, and the set watchdog-time-
out input (SWT) is set to (V
CC
- 0.6V) if it is not already
connected to V
CC
(for internal timeouts). The chip-
enable transmission gate is also disabled while reset is
asserted; the chip-enable input (CE IN) becomes high
impedance and the chip-enable output (CE OUT) is
pulled up to V
CC
.
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MAXIM [ MAXIM INTEGRATED PRODUCTS ]
