TABLE I. Electrical performance characteristics - Continued.
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Test
|Symbol
Conditions
+125 C
= 0 V; 4.5 V
| Group A | Device
|subgroups | types
Limits
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| Unit
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|t
|t
| -55 C
T
|
C
| V
V
5.5 V
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| Min | Max
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SS
CC
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unless otherwise specified
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| 01-07
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Data hold time
Byte load cycle
|See figures 4, 5, and 6 as
|9, 10, 11
| 16-19
| 10
| 0
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|
| ns
WHDX
EHDX
| applicable. 5/
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| 08-15
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|t
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|9, 10, 11
| 01-15
| .20
| 149
| µs
WHWL2
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| 16-19
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| .3
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| 30
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|01-02,16 |
|03-04,17 |
|05-06,18 |
| 250
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| 200
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Last byte loaded to data
polling
|t
|t
|
|9, 10, 11
| 150
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WHEL
EHEL
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|07,08,
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| 120
| ns
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|13,19
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|09,10,
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| 90
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|14
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|11,12,
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| 70
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|15
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CE setup time
(chip erase)
|t
|See figures 4, 5, and 6 as
|9, 10, 11
| 01-15
| 5
|
| µs
ELWL
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| applicable. 5/ 6/
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OE setup time
(chip erase)
|t
|9, 10, 11
| 01-15
| 5
|
| µs
OVHWL
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| 01-07
| 10
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| ms
WE pulse width (chip
erase)
|t
|9, 10, 11
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WLWH2
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| 08-15
| 10
|
| µs
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CE hold time
(chip erase)
|t
|9, 10, 11
| 01-15
| 5
|
| µs
WHEH
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OE hold time (chip erase)
|t
|
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|9, 10, 11
| 01-15
| 5
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| µs
WHOH
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High voltage
(chip erase)
|V
|9, 10, 11
| 01-15
| 12
| 13
| V
H
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Clear recovery
(chip erase)
|t
|9, 10, 11
| 01-15
|
| 50
| ms
OLEL
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Data setup time
(chip erase) 7/
|t
|9, 10, 11
| 01-15
| 1
| µs
DHWL
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Data hold time during
chip erase cycle 7/
|t
|
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|9, 10, 11
| 01-15
| 1
| µs
WHDX
|
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See footnotes at end of table.
SIZE
STANDARD
5962-38267
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
G
SHEET
11
DSCC FORM 2234
APR 97
MAXWELL [ MAXWELL TECHNOLOGIES ]
