12-Bit Buffered Multiplying
Digital to Analog Converter
T
ABLE
3. D
ELTA
L
IMITS
P
ARAMETER
I
DD
V
ARIATION
±10%
7545B
T
ABLE
4. 7545B S
PECIFICATIONS
(V
DD
= +5 V ±10%, T
A
= -55
TO
125
°
C
UNLESS OTHERWISE NOTED
)
T
EST
Resolution
Relative Accuracy
Differential Nonlinearity
Gain Error
1
Gain Temperature Coefficient
2
Power Supply Rejection
Output Current Settling Time
2
S
YMBOL
T
EST
C
ONDITION
RES
RA
DNL
A
E
TC
AE
PSRR
t
SL
V
DD
= 5%
To 1/2LSB; OUT1 Load = 100
Ω
,
DAC Output Measured from Fall-
ing Edge of WR. CS = 0V
12-Bit Monotonic T
MIN
to T
MAX
DAC Register Loaded with 1111
1111 1111
S
UBGROUPS
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
M
IN
12
-1/2
-1
-4
-5
-0.004
--
M
AX
--
1/2
1
4
5
0.004
2
U
NIT
Bits
LSB
LSB
LSB
ppm/
°
C
Memory
%/%
µs
Feed through Error
Reference Input Resistance
(Pin 19 to Ground)
2
Digital Input High Voltage
Digital Input Low Voltage
Digital Input Leakage Current
Digital Input Capacitance
2
Output Capacitance
2
FT
R
IN
V
IH
V
IL
I
IN
C
IN
C
OUT1
t
CS
t
CH
t
WR
t
DS
t
DH
I
DD
All Digital Inputs V
IL
or V
IH
All Digital Inputs 0 or V
DD
V
IN
= 0 V or V
DD
DB0 - DB11; WR, CS
DB0 - DB11 = 0 V, WR, CS = 0V
DB0 - DB11 = V
DD
, WR, CS = 0V
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
1, 2, 3
1, 2, 3
5 (typical)
10
2.4
--
-10
--
--
--
380
0
400
210
10
--
--
25
--
0.8
10
20
70
200
--
--
--
--
--
2
500
mV p-p
K
Ω
V
V
µA
pF
pF
Chip Select to Write Setup
Time
2
Chip Select to Write Hold Time
2
Write Pulse Width
2
Data Setup Time
2
Data Hold Time
2
Supply Current from V
DD
t
CS
> t
WR
, t
CH
> 0
nS
mA
µA
1. Measured using feedback resistor.
2. Guaranteed by design.
07.26.07 Rev 1
All data sheets are subject to change without notice
3
©2007 Maxwell Technologies
All rights reserved.
MAXWELL [ MAXWELL TECHNOLOGIES ]
