16 Megabit (512K x 32-Bit) MCM SRAM
89C1632
3. t
HZ
and t
OHZ
are defined as the time at which the outputs achieve the open circuit condition and are not referenced to V
OH
or
V
OL
levels.
4. At any given temperature and voltage conditions, t
HZ
(max) is less than t
LZ
(min) both for a given device and from device to
device.
5. Transition is measured +200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.
6. Device is continuously selected with CS = V
IL
.
7. Address valid prior to coincident with CS transition low.
8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write
cycle.
F
IGURE
4. T
IMING
W
AVEFORM OF
W
RITE
C
YCLE (1)
(OE C
LOCK
)
Memory
F
IGURE
5. T
IMING
W
AVEFORM OF
W
RITE
C
YCLE (2)
(OE L
OW
F
IIXED
)
01.10.05 Rev 3
All data sheets are subject to change without notice
8
©2005 Maxwell Technologies.
All rights reserved.
MAXWELL [ MAXWELL TECHNOLOGIES ]
