1 Gb (8-Meg X 32-Bit X 4-Banks) SDRAM
T
ABLE
4. DC E
LECTRICAL
C
HARACTERISTICS
97SD3232
S
UBGROUPS
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
440
580
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
-2
-4
-1.5
2.4
880
12
2
4
1.5
mA
mA
uA
uA
uA
V
M
IN
M
AX
80
36
16
12
120
60
U
NITS
mA
mA
mA
mA
mA
mA
mA
(V
CC
= 3.3V + 0.3V, V
CC
Q = 3.3V + 0.3V, T
A
= -55
TO
125°C,
UNLESS OTHERWISE SPECIFIED
)
P
ARAMETER
Standby Current in non power down
6
Standby Current in non power down
7
( Input signal stable)
Active standby current in
1,2,4
power down
Active standby current in power down
(input signal stable)
2,5
Active standby power in non power
down
1,2,6
Active standby current in non power
down ( input signal stable)
2,7
Burst Operating Current
1,2,8
CAS Latency = 2
CAS Latency = 3
Refresh Current
3
Self Refresh current
9
Input Leakage Current - CLK
Input Leakage Current - All Other
Output Leakage Current
Output high voltage
S
YMBOL
I
CC2N
I
CC2NS
I
CC3P
I
CC3PS
I
CC3N
I
CC3NS
I
CC4
T
EST
C
ONDITIONS
CKE, CS = V
IH
t
CK
= 12 ns
CKE = V
IH
t
CK
= 0
CKE = V
IL
t
CK
= 12 ns
CKE = V
IL
t
CK
= 0
CKE, CS1-4 = V
IH
t
CK
= 12 ns
CKE = V
IH
t
CK
= 0
t
CK
= min
BL = 4
t
RC
= min
V
IH
>V
CC
- 0.2V
V
IL
< 0.2 V
0<V
LI
<V
CC
0<V
LI
<V
CC
0<V
LO
<V
CC
I
OH
= -4mA
Memory
I
CC5
I
CC6
I
LI
I
LI
I
LO
V
OH
I
OL
= 4 mA
1, 2, 3
0.4
V
Output low voltage
V
OL
1. I
CC1
depends on output load conditions when the device is selected. I
CC1
(max) is specified with the output open.
2. One Bank Operation
3. Input signals are changed once per clock.
4. After power down mode, CLK operating current.
5. After power down mode, no CLK operating current.
6. Input signals are changed once per two clocks.
7. Input signals for V
IH
or V
IL
are fixed.
8. Input signals are changed once per four clocks.
9. After self refresh mode set, self refresh current. Use Self Refresh for temperatures less than 70
°C O
NLY
01.11.05 Rev 2
All data sheets are subject to change without notice
4
©2005 Maxwell Technologies
All rights reserved.