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MX25L1605DZNI-12G 参数 Datasheet PDF下载

MX25L1605DZNI-12G图片预览
型号: MX25L1605DZNI-12G
PDF下载: 下载PDF文件 查看货源
内容描述: 16M - BIT [X 1 / X 2 ] CMOS串行闪存 [16M-BIT [x 1 / x 2] CMOS SERIAL FLASH]
分类和应用: 闪存存储内存集成电路光电二极管时钟
文件页数/大小: 56 页 / 994 K
品牌: MCNIX [ MACRONIX INTERNATIONAL ]
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MX25L1605D
MX25L3205D
MX25L6405D
Table 2. Protected Area Sizes
Status bit
BP3 BP2 BP1 BP0 16Mb
0
0
0
0 0(none)
0
0
0
1 1(1block, block 31th)
0
0
1
0 2(2blocks, block 30th-31th)
0
0
1
1 3(4blocks, block 28th-31th)
0
1
0
0 4(8blocks, block 24th-31th)
0
1
0
1 5(16blocks, block 16th-31th)
0
1
1
0 6(32blocks, all)
0
1
1
1 7(32blocks, all)
1
0
0
0 8(32blocks, all)
1
0
0
1 9(32blocks, all)
1
0
1
0 10(16blocks, block 0th-15th)
1
0
1
1 11(24blocks, block 0th-23th)
1
1
0
0 12(28blocks, block 0th-27th)
1
1
0
1 13(30blocks, block 0th-29th)
1
1
1
0 14(31blocks, block 0th-30th)
1
1
1
1 15(32blocks, all)
Protect Level
32Mb
0(none)
1(1block, block 63th)
2(2blocks, block 62th-63th)
3(4blocks, block 60th-63th)
4(8blocks, block 56th-63th)
5(16blocks, block 48th-63th)
6(32blocks, block 32th-63th)
7(64blocks, all)
8(64blocks, all)
9(32blocks, block 0th-31th)
10(48blocks, block 0th-47th)
11(56blocks, block 0th-55th)
12(60blocks, block 0th-59th)
13(62blocks, block 0th-61th)
14(63blocks, block 0th-62th)
15(64blocks, all)
64Mb
0(none)
1(2blocks, block 126th-127th)
2(4blocks, block 124th-127th)
3(8blocks, block 120th-127th)
4(16blocks, block 112th-127th)
5(32blocks, block 96th-127th)
6(64blocks,block 64th-127th)
7(128blocks, all)
8(128blocks, all)
9(64blocks, block 0th-63th)
10(96blocks, block 0th-95th)
11(112blocks, block 0th-111th)
12(120blocks, block 0th-119th)
13(124blocks, block 0th-123th)
14(126blocks, block 0th-125th)
15(128blocks, all)
II. Additional 512-bit secured OTP
for unique identifier: to provide 512-bit one-time program area for setting device
unique serial number - Which may be set by factory or system customer. Please refer to table 3. 512-bit secured OTP
definition.
- Security register bit 0 indicates whether the chip is locked by factory or not.
- To program the 512-bit secured OTP by entering 512-bit secured OTP mode (with ENSO command), and going through
normal program procedure, and then exiting 512-bit secured OTP mode by writing EXSO command.
- Customer may lock-down the customer lockable secured OTP by writing WRSCUR(write security register) command
to set customer lock-down bit1 as "1". Please refer to table of "security register definition" for security register bit
definition and table of "512-bit secured OTP definition" for address range definition.
- Note: Once lock-down whatever by factory or customer, it cannot be changed any more. While in 512-bit secured OTP
mode, array access is not allowed.
Table 3. 512-bit Secured OTP Definition
Address range
xxxx00~xxxx0F
xxxx10~xxxx3F
Size
128-bit
384-bit
Standard
Factory Lock
ESN (electrical serial number)
N/A
Customer Lock
Determined by customer
P/N: PM1290
7
REV. 1.4, OCT. 01, 2008