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MX25L3205A 参数 Datasheet PDF下载

MX25L3205A图片预览
型号: MX25L3205A
PDF下载: 下载PDF文件 查看货源
内容描述: 32M - BIT [ ×1 ] CMOS串行eLiteFlashTM记忆 [32M-BIT [x 1] CMOS SERIAL eLiteFlashTM MEMORY]
分类和应用:
文件页数/大小: 46 页 / 954 K
品牌: MCNIX [ MACRONIX INTERNATIONAL ]
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MX25L3205A
Macronix NBit
TM
Memory Family
32M-BIT [x 1] CMOS SERIAL eLiteFlash
TM
MEMORY
FEATURES
GENERAL
• Serial Peripheral Interface (SPI) compatible -- Mode 0
and Mode 3
• 33,554,432 x 1 bit structure
• 64 Equal Sectors with 64K byte each
- Any sector can be erased
• Single Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program operations
• Latch-up protected to 100mA from -1V to Vcc +1V
• Low Vcc write inhibit is from 1.5V to 2.5V
PERFORMANCE
• High Performance
- Fast access time: 50MHz serial clock (30pF + 1TTL
Load)
- Fast program time: 3ms/page (typical, 256-byte per
page)
- Fast erase time: 1s/sector (typical, 64K-byte per
sector) and 64s/chip (typical)
- Acceleration mode:
- Program time: 2.4ms/page (typical)
- Erase time: 0.8s/sector (typical) and 51s/chip
(typical)
• Low Power Consumption
- Low active read current: 30mA (max.) at 50MHz
- Low active programming current: 30mA (max.)
- Low active erase current: 38mA (max.)
- Low standby current: 50uA (max.)
- Deep power-down mode 1uA (typical)
• Minimum 10K erase/program cycle for array
• Minimum 100K erase/program cycle for additional 4Kb
SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code
• Auto Erase and Auto Program Algorithm
-
Automatically erases and verifies data at selected
sector
-
Automatically programs and verifies data at selected
page by an internal algorithm that automatically times
the program pulse widths (Any page to be programed
should have page in the erased state first)
Status Register Feature
Electronic Identification
-
JEDEC 2-byte Device ID
- RES command, 1-byte Device ID
- REMS command, ADD=00H will output the
manufacturer's ID first and ADD=01H will output device
ID first
Additional 4Kb sector independent from main memory
for parameter storage to eliminate EEPROM from
system
HARDWARE FEATURES
SCLK Input
-
Serial clock input
• SI Input
-
Serial Data Input
• SO/PO7
- Serial Data Output or Parallel mode Data output/input
• WP#/ACC Pin
-
Hardware write protection and Program/erase accel-
eration
• HOLD# pin
-
pause the chip without disselecting the chip (not for
parallel mode, please connect HOLD# pin to VCC dur-
ing parallel mode)
• PO0~PO6
- for parallel mode data output/input
• PACKAGE
-
16-pin SOP (300mil)
- 8-land SON (8x6mm)
-
All Pb-free devices are RoHS Compliant
P/N: PM1243
REV. 1.2, NOV. 06, 2006
1