MX25L3205A
DATA PROTECTION
The MX25L3205A are designed to offer protection against
accidental erasure or programming caused by spurious
system level signals that may exist during power
transition. During power up the device automatically resets
the state machine in the Read mode. In addition, with its
control register architecture, alteration of the memory
contents only occurs after successful completion of
specific command sequences. The device also
incorporates several features to prevent inadvertent write
cycles resulting from VCC power-up and power-down
transition or system noise.
•
Power-on reset and tPUW: to avoid sudden power
switch by system power supply transition, the power-
on reset and tPUW (internal timer) may protect the
Flash.
other command to change data. The WEL bit will return
to reset stage under following situation:
- Power-up
- Write Disable (WRDI) command completion
- Write Status Register (WRSR) command completion
- Page Program (PP) command completion
- Sector Erase (SE) command completion
- Block Erase (BE) command completion
- Chip Erase (CE) command completion
•
Software Protection Mode (SPM): by using BP0-BP2
bits to set the part of Flash protected from data change.
Hardware Protection Mode (HPM): by using WP# going
low to protect the BP0-BP2 bits and SRWD bit from
data change.
Deep Power Down Mode: By entering deep power down
mode, the flash device also is under protected from
writing all commands except Release from deep power
down mode command (RDP) and Read Electronic
Signature command (RES).
•
• Valid command length checking: The command length
will be checked whether it is at byte base and com-
pleted on byte boundary.
• Write Enable (WREN) command: WREN command is
required to set the Write Enable Latch bit (WEL) before
•
P/N: PM1243
4
REV. 1.2, NOV. 06, 2006
MCNIX [ MACRONIX INTERNATIONAL ]
