MX25L8005M2I-15G 参数 Datasheet PDF下载

MX25L8005

HOLD FEATURE

HOLD# pin signal goes low to hold any serial communications with the device. The HOLD feature will not stop the operation

of write status register, programming, or erasing in progress.

The operation of HOLD requires Chip Select(CS#) keeping low and starts on falling edge of HOLD# pin signal while Serial

Clock (SCLK) signal is being low (if Serial Clock signal is not being low, HOLD operation will not start until Serial Clock

signal being low). The HOLD condition ends on the rising edge of HOLD# pin signal while Serial Clock(SCLK) signal is

being low( if Serial Clock signal is not being low, HOLD operation will not end until Serial Clock being low), see Figure 1.

Figure 1. Hold Condition Operation

CS#

SCLK

HOLD#

Hold

Condition

(standard)

Hold

Condition

(non-standard)

The Serial Data Output (SO) is high impedance, both Serial Data Input (SI) and Serial Clock (SCLK) are don't care during

the HOLD operation. If Chip Select (CS#) drives high during HOLD operation, it will reset the internal logic of the device.

To re-start communication with chip, the HOLD# must be at high and CS# must be at low.

P/N: PM1237

6

REV. 2.2, OCT. 23, 2008