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MX28F2000PQC-12C4 参数 Datasheet PDF下载

MX28F2000PQC-12C4图片预览
型号: MX28F2000PQC-12C4
PDF下载: 下载PDF文件 查看货源
内容描述: 2M- BIT [ 256K ×8 ] CMOS FLASH MEMORY [2M-BIT [256K x 8] CMOS FLASH MEMORY]
分类和应用:
文件页数/大小: 33 页 / 192 K
品牌: MCNIX [ MACRONIX INTERNATIONAL ]
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MX28F2000P
2M-BIT [256K x 8] CMOS FLASH MEMORY
FEATURES
• 262,144 bytes by 8-bit organization
• Fast access time: 70/90/120 ns
• Low power consumption
– 50mA maximum active current
– 100uA maximum standby current
• Programming and erasing voltage 12V
±
5%
• Command register architecture
– Byte Programming (15us typical)
– Auto chip erase 5 seconds typical
(including preprogramming time)
– Block Erase
• Optimized high density blocked architecture
– Four 4-KB blocks (Top)
– Fourteen 16-KB blocks
– Four 4-KB blocks (Bottom)
• Auto Erase (chip & block) and Auto Program
– DATA polling
– Toggle bit
• 10,000 minimum erase/program cycles
• Latch-up protected to 100mA from -1 to VCC+1V
• Advanced CMOS Flash memory technology
• Compatible with JEDEC-standard byte-wide 32-pin
EPROM pinouts
• Package type:
– 32-pin plastic DIP
– 32-pin PLCC
– 32-pin TSOP (Type 1)
GENERAL DESCRIPTION
The MX28F2000P is a 2-mega bit Flash memory or-
ganized as 256K bytes of 8 bits each. MXIC's Flash
memories offer the most cost-effective and reliable
read/write non-volatile random access memory. The
MX28F2000P is packaged in 32-pin PDIP, PLCC
and TSOP. It is designed to be reprogrammed and
erased in-system or in-standard EPROM program-
mers.
The standard MX28F2000P offers access times as
fast as 70 ns, allowing operation of high-speed
microprocessors without wait states. To eliminate
bus contention, the MX28F2000P has separate chip
enable (CE) and output enable (OE ) controls.
MXIC's Flash memories augment EPROM function-
ality with in-circuit electrical erasure and
programming. The MX28F2000P uses a command
register to manage this functionality, while
maintaining a standard 32-pin pinout. The
command register allows for 100% TTL level control
inputs and fixed power supply levels during erase
and programming, while maintaining maximum
EPROM compatibility.
MXIC Flash technology reliably stores memory con-
tents even after 10,000 erase and program cycles.
The MXIC cell is designed to optimize the erase and
programming mechanisms. In addition, the combi-
nation of advanced tunnel oxide processing and low
internal electric fields for erase and programming
operations produces reliable cycling.
The
MX28F2000P uses a 12.0V
±
5% VPP supply to
perform the Auto Program/Erase algorithms.
The highest degree of latch-up protection is
achieved with MXIC's proprietary non-epi process.
Latch-up protection is proved for stresses up to 100
milliamps on address and data pin from -1V to VCC
+ 1V.
P/N: PM0380
1
REV. 1.5, OCT 29, 1998