MX29F001T/B
1M-BIT [128K x 8] CMOS FLASH MEMORY
FEATURES
•
•
•
•
5.0V
±
10% for read, erase and write operation
131072x8 only organization
Fast access time: 55/70/90/120ns
Low power consumption
– 30mA maximum active current(5MHz)
– 1u
A
typical standby current
• Command register architecture
– Byte Programming (7us typical)
– Sector Erase (8K-Byte x1,4K-Byte x 2, 8K Bytex2,
32K-Bytex1, and 64K-Byte x1)
• Auto Erase (chip & sector) and Auto Program
– Automatically erase any combination of sectors
with Erase Suspend capability.
– Automatically programs and verifies data at speci
fied address
• Erase Suspend/Erase Resume
– Suspends an erase operation to read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation.
• Status Reply
– Data polling & Toggle bit for detection of program
and erase cycle completion.
• Chip protect/unprotect for 5V only system or 5V/12V
system
• 100,000 minimum erase/program cycles
• Latch-up protected to 100mA from -1 to VCC+1V
• Boot Code Sector Architecture
– T = Top Boot Sector
– B = Bottom Boot Sector
• Low VCC write inhibit is equal to or less than 3.2V
• Package type:
– 32-pin PLCC
– 32-pin TSOP
– 32-pin PDIP
• Boot Code Sector Architecture
– T=Top Boot Sector
– B=Bottom Boot Sector
• 20 years data retention
GENERAL DESCRIPTION
The MX29F001T/B is a 1-mega bit Flash memory
organized as 128K bytes of 8 bits only MXIC's Flash
memories offer the most cost-effective and reliable
read/write non-volatile random access memory. The
MX29F001T/B is packaged in 32-pin PLCC, TSOP,
PDIP. It is designed to be reprogrammed and
erased in-system or in-standard EPROM program-
mers.
The standard MX29F001T/B offers access time as
fast as 55ns, allowing operation of high-speed micro-
processors without wait states. To eliminate bus
contention, the MX29F001T/B has separate chip
enable (CE) and output enable (OE) controls.
MXIC's Flash memories augment EPROM function-
ality with in-circuit electrical erasure and
programming. The MX29F001T/B uses a command
register to manage this functionality. The command
register allows for 100% TTL level control inputs and
fixed power supply levels during erase and
programming, while maintaining maximum EPROM
compatibility.
MXIC Flash technology reliably stores memory con-
tents even after 100,000 erase and program cycles.
The MXIC cell is designed to optimize the erase and
programming mechanisms. In addition, the combi-
nation of advanced tunnel oxide processing and low
internal electric fields for erase and programming
operations produces reliable cycling.
The
MX29F001T/B uses a 5.0V
±
10% VCC supply to
perform the High Reliability Erase and auto
Program/Erase algorithms.
The highest degree of latch-up protection is
achieved with MXIC's proprietary non-epi process.
Latch-up protection is proved for stresses up to 100
milliamps on address and data pin from -1V to VCC
+ 1V.
P/N: PM0515
1
REV. 2.1, JUN. 14, 2001
MCNIX [ MACRONIX INTERNATIONAL ]
