MX29F002/002N
Q3
Sector Erase Timer
After the completion of the initial sector erase command
sequence th sector erase time-out will begin. Q3 will
remain low until the time-out is complete. Data Polling and
Toggle Bit are valid after the initial sector erase command
sequence.
If Data Polling or the Toggle Bit indicates the device has
been written with a valid erase command, Q3 may be used
to determine if the sector erase timer window is still open.
If Q3 is high ("1") the internally controlled erase cycle has
begun; attempts to write subsequent commands to the
device will be ignored until the erase operation is completed
as indicated by Data Polling or Toggle Bit. If Q3 is low ("0"),
the device will accept additional sector erase commands.
To insure the command has been accepted, the system
software should check the status of Q3 prior to and
following each subsequent sector erase command. If Q3
were high on the second status check, the command may
not have been accepted.
LOGICAL INHIBIT
Writing is inhibited by holding any one of OE = VIL, CE =
VIH or WE = VIH. To initiate a write cycle CE and WE must
be a logical zero while OE is a logical one.
POWER SUPPLY DECOUPLING
In order to reduce power switching effect, each device
should have a 0.1uF ceramic capacitor connected between
its VCC and GND.
SECTOR PROTECTION WITH 12V SYSTEM
The MX29F002T/B features hardware sector protection.
This feature will disable both program and erase operations
for these sectors protected. To activate this mode, the
programming equipment must force VID on address pin
A9 and control pin OE, (suggest VID = 12V) A6 = VIL and
CE = VIL.(see Table 2) Programming of the protection
circuitry begins on the falling edge of the WE pulse and is
terminated on the rising edge. Please refer to sector
protect algorithm and waveform.
To verify programming of the protection circuitry, the
programming equipment must force VID on address pin
A9 ( with CE and OE at VIL and WE at VIH. When A1=1,
it will produce a logical "1" code at device output Q0 for a
protected sector. Otherwise the device will produce 00H
for the unprotected sector. In this mode, the
addresses,except for A1, are in "don't care" state. Address
locations with A1 = VIL are reserved to read manufacturer
and device codes.(Read Silicon ID)
It is also possible to determine if the sector is protected in
the system by writing a Read Silicon ID command.
Performing a read operation with A1=VIH, it will produce
a logical "1" at Q0 for the protected sector.
DATA PROTECTION
The MX29F002T/B is designed to offer protection against
accidental erasure or programming caused by spurious
system level signals that may exist during power transition.
During power up the device automatically resets the state
machine in the Read mode. In addition, with its control
register architecture, alteration of the memory contents
only occurs after successful completion of specific
command sequences. The device also incorporates
several features to prevent inadvertent write cycles
resulting from VCC power-up and power-down transition
or system noise.
WRITE PULSE "GLITCH" PROTECTION
Noise pulses of less than 5ns(typical) on CE or WE will not
initiate a write cycle.
P/N: PM0547
REV. 1.1, JUN. 14, 2001
12
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