欢迎访问ic37.com |
会员登录 免费注册
发布采购

MX29LV400TTC-90 参数 Datasheet PDF下载

MX29LV400TTC-90图片预览
型号: MX29LV400TTC-90
PDF下载: 下载PDF文件 查看货源
内容描述: 4M- BIT [ 512K ×8 / 256K ×16 ]的CMOS单电压3V仅限于Flash存储器 [4M-BIT [512K x 8 / 256K x 16] CMOS SINGLE VOLTAGE 3V ONLY FLASH MEMORY]
分类和应用: 闪存存储内存集成电路光电二极管
文件页数/大小: 59 页 / 1217 K
品牌: Macronix [ MACRONIX INTERNATIONAL ]
 浏览型号MX29LV400TTC-90的Datasheet PDF文件第11页浏览型号MX29LV400TTC-90的Datasheet PDF文件第12页浏览型号MX29LV400TTC-90的Datasheet PDF文件第13页浏览型号MX29LV400TTC-90的Datasheet PDF文件第14页浏览型号MX29LV400TTC-90的Datasheet PDF文件第16页浏览型号MX29LV400TTC-90的Datasheet PDF文件第17页浏览型号MX29LV400TTC-90的Datasheet PDF文件第18页浏览型号MX29LV400TTC-90的Datasheet PDF文件第19页  
MX29LV400T/B  
If a program address falls within a protected sector, Q6  
toggles for approximately 2 us after the program com-  
mand sequence is written, then returns to reading array  
data.  
high. If the toggle bit is no longer toggling, the device  
has successfuly completed the program or erase opera-  
tion. If it is still toggling, the device did not complete the  
operation successfully, and the system must write the  
reset command to return to reading array data.  
Q6 also toggles during the erase-suspend-program mode,  
and stops toggling once the Automatic Program algo-  
rithm is complete.  
The remaining scenario is that system initially determines  
that the toggle bit is toggling and Q5 has not gone high.  
The system may continue to monitor the toggle bit and  
Q5 through successive read cycles, determining the sta-  
tus as described in the previous paragraph. Alterna-  
tively, it may choose to perform other system tasks. In  
this case, the system must start at the beginning of the  
algorithm when it returns to determine the status of the  
operation.  
Table 7 shows the outputs for Toggle Bit I on Q6.  
Q2:Toggle Bit II  
The "Toggle Bit II" on Q2, when used with Q6, indicates  
whether a particular sector is actively eraseing (that is,  
the Automatic Erase alorithm is in process), or whether  
that sector is erase-suspended. Toggle Bit II is valid  
after the rising edge of the final WE or CE, whichever  
happens first, in the command sequence.  
Q5  
ExceededTiming Limits  
Q5 will indicate if the program or erase time has ex-  
ceeded the specified limits(internal pulse count). Under  
these conditions Q5 will produce a "1". This time-out  
condition indicates that the program or erase cycle was  
not successfully completed. Data Polling andToggle Bit  
are the only operating functions of the device under this  
condition.  
Q2 toggles when the system reads at addresses within  
those sectors that have been selected for erasure. (The  
system may use either OE or CE to control the read  
cycles.) But Q2 cannot distinguish whether the sector  
is actively erasing or is erase-suspended. Q6, by com-  
parison, indicates whether the device is actively eras-  
ing, or is in Erase Suspend, but cannot distinguish which  
sectors are selected for erasure. Thus, both status bits  
are required for sectors and mode information. Refer to  
Table 7 to compare outputs for Q2 and Q6.  
If this time-out condition occurs during sector erase op-  
eration, it specifies that a particular sector is bad and it  
may not be reused. However, other sectors are still func-  
tional and may be used for the program or erase opera-  
tion. The device must be reset to use other sectors.  
Write the Reset command sequence to the device, and  
then execute program or erase command sequence. This  
allows the system to continue to use the other active  
sectors in the device.  
Reading Toggle Bits Q6/ Q2  
Whenever the system initially begins reading toggle bit  
status, it must read Q7-Q0 at least twice in a row to  
determine whether a toggle bit is toggling. Typically, the  
system would note and store the value of the toggle bit  
after the first read. After the second read, the system  
would compare the new value of the toggle bit with the  
first. If the toggle bit is not toggling, the device has  
completed the program or erase operation. The system  
can read array data on Q7-Q0 on the following read cycle.  
If this time-out condition occurs during the chip erase  
operation, it specifies that the entire chip is bad or com-  
bination of sectors are bad.  
If this time-out condition occurs during the byte program-  
ming operation, it specifies that the entire sector con-  
taining that byte is bad and this sector maynot be re-  
used, (other sectors are still functional and can be re-  
used).  
However, if after the initial two read cycles, the system  
determines that the toggle bit is still toggling, the sys-  
tem also should note whether the value of Q5 is high  
(see the section on Q5). If it is, the system should then  
determine again whether the toggle bit is toggling, since  
the toggle bit may have stopped toggling just as Q5 went  
The time-out condition will not appear if a user tries to  
program a non blank location without erasing. Please  
note that this is not a device failure condition since the  
device was incorrectly used.  
P/N:PM0710  
REV. 1.4, NOV. 23, 2001  
15