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MX29LV400BXEC-70 参数 Datasheet PDF下载

MX29LV400BXEC-70图片预览
型号: MX29LV400BXEC-70
PDF下载: 下载PDF文件 查看货源
内容描述: 4M- BIT [ 512K ×8 / 256K ×16 ]的CMOS单电压3V仅限于Flash存储器 [4M-BIT [512K x 8 / 256K x 16] CMOS SINGLE VOLTAGE 3V ONLY FLASH MEMORY]
分类和应用: 存储
文件页数/大小: 59 页 / 1217 K
品牌: MCNIX [ MACRONIX INTERNATIONAL ]
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MX29LV400T/B
4M-BIT [512K x 8 / 256K x 16] CMOS SINGLE VOLTAGE
3V ONLY FLASH MEMORY
FEATURES
• Extended single - supply voltage range 2.7V to 3.6V
• 524,288 x 8/262,144 x 16 switchable
• Single power supply operation
- 3.0V only operation for read, erase and program
operation
• Fast access time: 55R/70/90ns
• Low power consumption
- 20mA maximum active current
- 0.2uA typical standby current
• Command register architecture
- Byte/word Programming (9us/11us typical)
- Sector Erase (Sector structure 16K-Byte x 1,
8K-Byte x 2, 32K-Byte x1, and 64K-Byte x7)
• Auto Erase (chip & sector) and Auto Program
- Automatically erase any combination of sectors with
Erase Suspend capability.
- Automatically program and verify data at specified
address
• Erase suspend/Erase Resume
- Suspends sector erase operation to read data from,
or program data to, any sector that is not being erased,
then resumes the erase.
• Status Reply
- Data polling & Toggle bit for detection of program and
erase operation completion.
• Ready/Busy pin (RY/BY)
- Provides a hardware method of detecting program or
erase operation completion.
• Sector protection
- Hardware method to disable any combination of
sectors from program or erase operations
- Tempoary sector unprotect allows code changes in
previously locked sectors.
• 100,000 minimum erase/program cycles
• Latch-up protected to 100mA from -1V to VCC+1V
• Boot Sector Architecture
- T = Top Boot Sector
- B = Bottom Boot Sector
• Low VCC write inhibit is equal to or less than 2.3V
• Package type:
- 44-pin SOP
- 48-pin TSOP
- 48-ball CSP
• Compatibility with JEDEC standard
- Pinout and software compatible with single-power
supply Flash
GENERAL DESCRIPTION
The MX29LV400T/B is a 4-mega bit Flash memory or-
ganized as 512K bytes of 8 bits or 256K words of 16
bits. MXIC's Flash memories offer the most cost-effec-
tive and reliable read/write non-volatile random access
memory. The MX29LV400T/B is packaged in 44-pin
SOP, 48-pin TSOP and 48-ball CSP. It is designed to be
reprogrammed and erased in system or in standard
EPROM programmers.
The standard MX29LV400T/B offers access time as fast
as 55ns, allowing operation of high-speed microproces-
sors without wait states. To eliminate bus contention,
the MX29LV400T/B has separate chip enable (CE) and
output enable (OE) controls.
MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
MX29LV400T/B uses a command register to manage
this functionality. The command register allows for 100%
TTL level control inputs and fixed power supply levels
during erase and programming, while maintaining maxi-
mum EPROM compatibility.
MXIC Flash technology reliably stores memory contents
even after 100,000 erase and program cycles. The MXIC
cell is designed to optimize the erase and programming
mechanisms. In addition, the combination of advanced
tunnel oxide processing and low internal electric fields
for erase and program operations produces reliable cy-
cling. The MX29LV400T/B uses a 2.7V~3.6V VCC sup-
ply to perform the High Reliability Erase and auto Pro-
gram/Erase algorithms.
The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up pro-
tection is proved for stresses up to 100 milliamps on
address and data pin from -1V to VCC + 1V.
P/N:PM0710
REV. 1.4, NOV. 23, 2001
1