ADVANCED INFORMATION
MX98715AEC-D
SINGLE CHIP FAST ETHERNET NIC CONTROLLER
1. FEATURES
• A single chip solution integrates 100/10 Base-T fast
Ethernet MAC, PHY and PMD
• Microsoft PC97, 98, 99 and Novell 4.11/5.0 certified.
• Support DMI 2.0 management.
• Support Intel PXE remote boot device.
• Fully comply to IEEE 802.3u specification
• Operates over 100 meters of STP and cat 5 UTP cable
• Fully comply to PCI spec. 2.1 up to 33MHz
• Fully comply to Advanced Configuration and Power
Interface (ACPI) Rev 1.1
• Fully comply to PCI Bus Power Management Inter-
face spec. Rev 1.1
• Support full and half duplex operations in both 100
Base-TX and 10 Base-T mode
• Supports 3 kinds of wake up events defined in Net-
work Device Class Power Management Spec 1.0.
Including:
- Magic Packet
- Link Change (link-on)
- Wake Up Frames
• Supports IEEE802.3x Frame Based Flow Control
scheme in full duplex mode.
• Supports early interrupt on both transmit and receive
operations. • 100/10 Base-T NWAY auto-negotiation
function
• Large on-chip FIFOs for both transmit and receive
operations without external local memory
• Bus master architecture with linked host buffers deliv-
ers the most optimized performance
• 32-bit bus master DMA channel provides ultra low
CPU utilization suitable for server and windows appli-
cations.
• Proprietary Adaptive Network Throughput Control
(ANTC) technology to optimize data integrity and
throughput
• Support up to 64K bytes boot ROM interface
• Three levels of loopback diagnositic capability
• Support a variety of flexible address filtering modes
with 16 CAM addresses and 128 bits hash
• MicroWire interface to EEPROM for customer's IDs
and configuration data
• Single +5V power supply, CMOS technology, 128-pin
PQFP package.
( Magic packet technology is a trademark of advanced Micro De-
vice Corp. )
2. GENERAL DESCRIPTIONS
The MX98715AEC-D controller is an IEEE802.3u com-
pliant single chip 32-bit full duplex, 10/100Mbps highly
integrated Fast Ethernet combo solution, designed to
address high performance local area networking (LAN)
system application requirements.
MX98715AEC-D's PCI bus master architecture delivers
the optimized performance for future high speed and pow-
erful processor technologies. In other words, the
MX98715AEC-D not only keeps CPU utilization low while
maximizing data throughput, but it also optimizes the
PCI bandwidth providing the highest PCI bandwidth uti-
lization. To further reduce maintenance costs the
MX98715AEC-D uses drivers that are backward com-
patible with the original MXIC MX98715 series control-
lers.
The MX98715AEC-D contains a PCI local bus glueless
interface, a Direct Memory Access (DMA) buffer man-
agement unit, an IEEE802.3u-compliant Media Access
Controller (MAC), large Transmit and Receive FIFOs, and
an on-chip 10 Base-T and 100 Base-TX transceiver sim-
plifying system design and improving high speed signal
quality. Full-duplex operation are supported in both 10
Base-T and 100 Base-TX modes that increases the
controller's operating bandwidth up to 200Mbps.
Equipped with intelligent IEEE802.3u-compliant auto-
negotiation, the MX98715AEC-D-based adapter allows
a single RJ-45 connector to link with the other
IEEE802.3u-compliant device without re-configuration.
P/N:PM0719
REV. 0.1 ,FEB. 05, 2001
1
MCNIX [ MACRONIX INTERNATIONAL ]
