1Gb: x4, x8, x16 DDR3 SDRAM
Operations
Precharge Power-Down (Precharge PD)
The precharge PD bit applies only when precharge power-down mode is being used.
When MR0[12] is set to “0,” the DLL is off during precharge power-down providing a
lower standby current mode; however,
t
XPDLL must be satisfied when exiting. When
MR0[12] is set to “1,” the DLL continues to run during precharge power-down mode to
enable a faster exit of precharge power-down mode; however,
t
XP must be satisfied when
exiting (see "Power-Down Mode" on page 151).
CAS Latency (CL)
The CL is defined by MR0[6:4], as shown in Figure 54 on page 110. CAS latency is the
delay, in clock cycles, between the internal READ command and the availability of the
first bit of output data. The CL can be set to 5, 6, 7, 8, 9, or 10. DDR3 SDRAM do not
support half-clock latencies.
Examples of CL = 6 and CL = 8 are shown in Figure 55. If an internal READ command is
registered at clock edge
n,
and the CAS latency is
m
clocks, the data will be available
nominally coincident with clock edge
n
+
m.
Figure 55: READ Latency
T0
CK#
CK
Command
READ
NOP
NOP
NOP
AL = 0, CL = 6
DQS, DQS#
DI
n
DI
n
+1
DI
n
+2
DI
n
+3
DI
n
+4
NOP
NOP
NOP
NOP
NOP
T1
T2
T3
T4
T5
T6
T7
T8
DQ
T0
CK#
CK
Command
READ
T1
T2
T3
T4
T5
T6
T7
T8
NOP
NOP
NOP
NOP
AL = 0, CL = 8
NOP
NOP
NOP
NOP
DQS, DQS#
DI
n
DQ
Transitioning Data
Don’t Care
Notes:
1. For illustration purposes, only CL = 6 and CL = 8 are shown. Other CL values are possible.
2. Shown with nominal
t
DQSCK and nominal
t
DSDQ.
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_4.fm - Rev. D 8/1/08 EN
112
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