1Gb: x4, x8, x16 DDR3 SDRAM
Output Characteristics and Operating Conditions
Table 44:
40Ω Output Driver Voltage and Temperature Sensitivity
Change
dR
ON
dTM
dR
ON
dVM
dR
ON
dTL
dR
ON
dVL
dR
ON
dTH
dR
ON
dVH
Min
0
0
0
0
0
0
Max
1.5
0.15
1.5
0.15
1.5
0.15
Unit
%/°C
%/mV
%/°C
%/mV
%/°C
%/mV
Output Characteristics and Operating Conditions
The DRAM uses both single-ended and differential output drivers. The single-ended
output driver is summarized in Table 45 while the differential output driver is summa-
rized in Table 46 on page 59.
Table 45:
Single-Ended Output Driver Characteristics
All voltages are referenced to Vss
Parameter/Condition
Output leakage current: DQ are disabled;
0V
≤
V
OUT
≤
V
DD
Q; ODT is disabled; ODT is HIGH
Output slew rate: Single-ended; For rising and falling
edges, measure between V
OL
(
AC
)
=
V
REF
- 0.1 × V
DD
Q and
V
OH
(
AC
) = V
REF
+ 0.1 × V
DD
Q
Single-ended DC high-level output voltage
Single-ended DC mid-point level output voltage
Single-ended DC low-level output voltage
Single-ended AC high-level output voltage
Single-ended AC low-level output voltage
Delta R
ON
between pull-up and pull-down for DQ/DQS
Test load for AC timing and output slew rates
Notes:
Symbol
I
OZ
SRQ
SE
Min
–5
2.5
Max
+5
5
Units
µA
V/ns
Notes
1
1, 2, 3
V
OH
(
DC
)
V
OM
(
DC
)
V
OL
(
DC
)
V
OH
(
AC
)
V
OL
(
AC
)
MM
PUPD
0.8 × V
DD
Q
0.5 × V
DD
Q
0.2 × V
DD
Q
V
TT
+ 0.1 × V
DD
Q
V
TT
- 0.1 × V
DD
Q
–10
+10
V
V
V
V
V
%
1, 2, 4
1, 2, 4
1, 2, 4
1, 2, 3, 5
1, 2, 3, 5
1, 6
3
Output to V
TT
(V
DD
Q/2) via 25Ω resistor
1. RZQ of 240Ω (±1 percent) with RZQ/7 enabled (default 34Ω driver) and is applicable after
proper ZQ calibration has been performed at a stable temperature and voltage
(V
DD
Q = V
DD
, V
SS
Q = V
SS
).
2. V
TT
= V
DD
Q/2.
3. See Figure 32 on page 60 for the test load configuration.
4. See Table 35 on page 55 for IV curve linearity. Do not use AC test load.
5. See Table 47 on page 61 for output slew rate.
6. See Table 35 on page 55 for additional information.
7. See Figure 30 on page 59 for an example of a single-ended output signal.
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_3.fm - Rev. D 8/1/08 EN
58
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