1Gb: x4, x8, x16 DDR3 SDRAM
Commands
Commands
Truth Tables
Table 62:
Truth Table – Command
Notes 1–5 apply to the entire table
CKE
Function
MODE REGISTER SET
REFRESH
Self refresh entry
Self refresh exit
Single-bank PRECHARGE
PRECHARGE all banks
Bank ACTIVATE
WRITE
BL8MRS,
BC4MRS
BC4OTF
BL8OTF
WRITE with BL8MRS,
auto
BC4MRS
precharge BC4OTF
BL8OTF
READ
BL8MRS,
BC4MRS
BC4OTF
BL8OTF
READ with
auto
precharge
BL8MRS,
BC4MRS
BC4OTF
BL8OTF
NO OPERATION
Device DESELECTED
Power-down entry
Power-down exit
ZQ CALIBRATION LONG
ZQ CALIBRATION SHORT
Notes:
Prev Next
BA
Symbol Cycle Cycle CS# RAS# CAS# WE# [2:0]
MRS
REF
SRE
SRX
PRE
PREA
ACT
WR
WRS4
WRS8
WRAP
WRAPS4
WRAPS8
RD
RDS4
RDS8
RDAP
RDAPS4
RDAPS8
NOP
DES
PDE
PDX
ZQCL
ZQCS
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
H
L
H
L
L
L
L
L
V
H
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
X
H
V
H
V
H
H
L
L
L
V
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
H
X
H
V
H
V
H
H
L
H
H
V
H
L
L
H
L
L
L
L
L
L
H
H
H
H
H
H
H
X
H
V
H
V
L
L
X
X
X
X
X
X
H
L
X
X
V
V
V
V
V
BA
V
BA
BA
BA
BA
BA
BA
BA
BA
BA
BA
BA
BA
BA
V
X
V
RFU
RFU
RFU
RFU
RFU
RFU
RFU
RFU
RFU
RFU
RFU
RFU
V
X
V
V
V
V
V
V
L
H
V
L
H
V
L
H
V
L
H
V
X
V
L
H
L
L
L
H
H
H
L
L
L
H
H
H
V
X
V
V
V
CA
CA
CA
CA
CA
CA
CA
CA
CA
CA
CA
CA
V
X
V
8
8
8
8
8
8
8
8
8
8
8
8
9
BA
V
V
V
V
V
V
An
A12
V
V
V
A10
V
V
V
A[11,
9:0]
V
V
V
Notes
OP code
Row address (RA)
1. Commands are defined by states of CS#, RAS#, CAS#, WE#, and CKE at the rising edge of the
clock. The MSB of BA, RA, and CA are device-density and configuration-dependent.
2. RESET# is LOW enabled and used only for asynchronous reset. Thus, RESET# must be held
HIGH during any normal operation.
3. The state of ODT does not affect the states described in this table.
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1Gb_DDR3_4.fm - Rev. D 8/1/08 EN
91
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