MDT1005
Instruction Code
111010 iiiiiiii
010111 trrrrrrr
011001 trrrrrrr
011010 trrrrrrr
011011 trrrrrrr
011100 trrrrrrr
011101 trrrrrrr
011110 trrrrrrr
010010 trrrrrrr
110100 iiiiiiii
010011 trrrrrrr
110101 iiiiiiii
010100 trrrrrrr
110110 iiiiiiii
011111 trrrrrrr
010110 trrrrrrr
Mnemonic
Operands
LDWI I
Function
Load immediate to W
Operating
I→W
[R(0~3)
↔
R(4~7)]→t
R + 1→t
R + 1→t
W + R→t
R
﹣W→t
(R+/W+1→t)
R
﹣1→t
R
﹣1→t
R
∩
W→t
i
∩
W→W
R
∪
W→t
i
∪
W→W
R
♁
W→t
i
♁
W→W
/R→t
R(n)→R(n-1), C→
R(7),
R(0)→C
R(n)→r(n+1),
C→R(0),
R(7)→C
0→W
0→R
0→R(b)
1→R(b)
Skip if R(b)=0
Skip if R(b)=1
n→PC,
PC+1→Stack
n→PC
n→PC,
PC+1→Stack
Stack→PC,i→W
n→PC
Status
None
None
Z
None
C, HC, Z
C, HC, Z
Z
None
Z
Z
Z
Z
Z
Z
Z
C
SWAPR R, t Swap halves register
INCR R, t
Increment register
INCRSZ R, t Increment register, skip if zero
ADDWR R, t Add W and register
SUBWR R, t Subtract W from register
DECR R, t
Decrement register
DECRSZ R, t Decrement register, skip if zero
ANDWR R, t AND W and register
ANDWI i
IORWR R, t
IORWI i
XORWI i
RRR
R, t
AND W and immediate
Inclu. OR W and register
Inclu. OR W and immediate
Exclu. OR W and immediate
Rotate right register
XORWR R, t Exclu. OR W and register
COMR R, t Complement register
010101 trrrrrrr
RLR
R, t
Rotate left register
C
010000 1xxxxxxx
010001 0rrrrrrr
0000bb brrrrrrr
0010bb brrrrrrr
0001bb brrrrrrr
0011bb brrrrrrr
1000nn nnnnnnnn
1010nn nnnnnnnn
110000 nnnnnnnn
110001 iiiiiiii
11001n nnnnnnnn
CLRW
CLRR
BCR
BSR
R
R, b
R, b
Clear working register
Clear register
Bit clear
Bit set
Bit Test, skip if clear
Bit Test, skip if set
Long CALL subroutine
Long JUMP to address
Call subroutine
Return, place immediate to W
JUMP to address
Z
Z
None
None
None
None
None
None
None
None
None
BTSC R, b
BTSS R, b
LCALL n
LJUMP n
CALL
RTWI
JUMP
n
i
n
This specification are subject to be changed without notice. Any latest information please preview
http;//www.mdtic.com.tw
P.7
2005/6
Ver1.4
MDTIC [ Micon Design Technology Corporation ]
