MDT10C23
12. Port A Equivalent Circuit
PA0-PA3
D
Q
I/O
Control
I/O
Control
Latch
C
K
Q
B
Port I/O
Pin
D
Data O/P
Latch
Write
G
QB
Input Resistor
Data
Bus
0
1
TTL input level
D
QB
G
Data I/P
Latch
+
-
S
Rea
d
VREF
comparator level
Compartor Control
PA4
D
Q
I/O
Control
Latch
I/O
Control
C
K
Q
B
Port I/O
Pin
D
G
Data O/P
Latch
Write
Q
B
Input Resistor
Data
Bus
comparator
enable
D
QB
G
Data I/P
Latch
Rea
d
TTL Input Level
3
2
1
3/4
VDD
1/2
VDD
1/4
VDD
Vref
0
S0 S1
CMR_4
CMR_5
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P. 13
2005/6 Ver. 1.2