MDT10C23
(B) Program Memory
Address
000- 7FF
7FF
Program memory
Description
The starting address of the power on, external reset or WDT
8. Reset Condition for all Registers
Register
CPIO A
CPIO B
TMR
IAR
RTCC
PC
STATUS
MSR
PORT A
PORT B
CMR
Address
－－
－－
－－
00h
01h
02h
03h
04h
05h
06h
07h
Power-On Reset
1111 1111
1111 1111
--11 1111
－
xxxx xxxx
1111 1111
0001 1xxx
100x xxxx
xxxx xxxx
xxxx xxxx
0000 0000
/MCLR Reset
1111 1111
1111 1111
--11 1111
－
uuuu uuuu
1111 1111
000# #uuu
100u uuuu
uuuuuuuu
uuuu uuuu
uuuu uuuu
WDT Reset
1111 1111
1111 1111
--11 1111
－
uuuu uuuu
1111 1111
000# #uuu
1uuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
Note : u＝unchanged, x＝unknown, -
＝unimplemented,
read as “0”
#＝value depends on the condition of the following table
Condition
/MCLR reset (not during SLEEP)
/MCLR reset during SLEEP
WDT reset (not during SLEEP)
WDT reset during SLEEP
Status: bit 4
U
1
0
0
Status: bit 3
u
0
1
0
9. Instruction Set
Instruction Code
010000 00000000
010000 00000001
010000 00000010
Mnemonic
Operands
NOP
CLRWT
SLEEP
Function
No operation
Clear Watchdog timer
Sleep mode
Operating
None
0→WT
0→WT, stop OSC
TF, PF
TF, PF
Status
This specification are subject to be changed without notice. Any latest information
please preview http;//www.mdtic.com.tw
P. 8
2005/6
Ver. 1.2
MDTIC [ Micon Design Technology Corporation ]
