MDT10P22(DF)
9. Instruction Set
Mnemonic
Operands
NOP
CLRWT
SLEEP
TMODE
RET
CPIO
STWR
LDR
LDWI I
SWAPR R, t
INCR
R, t
R
R
R, t
Instruction Code
010000 00000000
010000 00000001
010000 00000010
010000 00000011
010000 00000100
010000 00000rrr
010001 1rrrrrrr
011000 trrrrrrr
111010 iiiiiiii
010111 trrrrrrr
011001 trrrrrrr
011010 trrrrrrr
011011 trrrrrrr
011100 trrrrrrr
011101 trrrrrrr
011110 trrrrrrr
010010 trrrrrrr
110100 iiiiiiii
010011 trrrrrrr
110101 iiiiiiii
010100 trrrrrrr
110110 iiiiiiii
011111 trrrrrrr
010110 trrrrrrr
010101 trrrrrrr
010000 1xxxxxxx
010001 0rrrrrrr
0000bb brrrrrrr
Function
No operation
Clear Watchdog timer
Sleep mode
Return
Control I/O port register
Store W to register
Load register
Load immediate to W
Swap halves register
Increment register
Increment register, skip if
zero
Add W and register
Subtract W from register
Decrement register
Operating
None
0→WT
Status
TF, PF
None
None
r
None
None
Z
None
None
Z
None
C, HC, Z
C, HC, Z
Z
None
Z
Z
Z
Z
Z
Z
Z
C
C
Z
Z
None
0→WT, stop OSC TF, PF
Stack→PC
W→CPIO
W→R
R→t
I→W
[R(0~3)↔R(4~7)]
→t
R + 1→t
R + 1→t
W + R→t
R
﹣W→t
(R+/W+1→t)
R
﹣1→t
R
﹣1→t
R
∩
W→t
i
∩
W→W
R
∪
W→t
R
♁
W→t
i
♁
W→W
/R→t
R(n)
→R(n-1),
C
→R(7),
R(0)→C
R(n)→r(n+1),
C→R(0), R(7)→C
0→W
0→R
0→R(b)
Load W to TMODE register W→TMODE
INCRSZ R, t
ADDWR R, t
SUBWR R, t
DECR
R, t
DECRSZ R, t Decrement register, skip if
zero
ANDWR R, t AND W and register
ANDWI i
IORWR R, t
IORWI i
XORWR R, t
XORWI i
COMR
RRR
RLR
CLRW
CLRR
BCR
R
R, b
R, t
R, t
R, t
AND W and immediate
Inclu. OR W and register
Exclu. OR W and register
Exclu. OR W and
immediate
Complement register
Rotate right register
Rotate left register
Clear working register
Clear register
Bit clear
Inclu. OR W and immediate i
∪
W→W
This specification are subject to be changed without notice. Any latest information
please preview http;//www.mdtic.com.tw
P. 9
2007/8
Ver. 1.6
MDTIC [ Micon Design Technology Corporation ]
