P509(A)
M D T 1 0P509(A)
Security state
Security Disable
Power-edge Detect
PED Disable
PED Enable
(1.8V / 1.8V always enable / 2.1V always
enable)
(B) Program Memory
Security Enable
Address
000-3FF
000
Program memory
Description
The starting address of power on, external reset or WDT time-out reset.
8. Reset Condition for all Registers
Register
IAR
RTCC
PC
STATUS
MSR
OSCCON
PORT B
TMR
CPIO B
Address
00h
01h
02h
03h
04h
05h
06h
Power-On Reset
xxxx xxxx
xxxx xxxx
0000 0000
0001 1xxx
111x xxxx
0111 0000
--xx xxxx
1111 1111
--11 1111
/MCLR Reset
uuuu uuuu
uuuu uuuu
0000 0000
#00# #uuu
110u uuuu
0111 0000
--uu uuuu
1111 1111
--11 1111
WDT Reset
uuuu uuuu
uuuu uuuu
0000 0000
#00# #uuu
11uu uuuu
0111 0000
--uu uuuu
1111 1111
--11 1111
Note : u＝unchanged, x＝unknown, -
＝unimplemented,
read as “0”
#＝value depends on the condition of the following table
Condition
/MCLR reset (not during SLEEP)
/MCLR reset during SLEEP
WDT reset (not during SLEEP)
WDT reset during SLEEP
Wake-up from SLEEP on pin change
Status: bit 7
0
0
0
0
1
Status: bit 4
u
1
0
0
1
Status: bit 3
u
0
1
0
0
P.6
2010/7 PA
MDTIC [ Micon Design Technology Corporation ]
