MDT10P7401
(5) MSR (Memory Bank Select Register): R04
Memory Bank Select Register
0: 00h~7Fh (Bank0)
1: 80h~FFh (Bank1)
b7
b6
b5
b4
b3
b2
b1
b0
Indirect Addressing Mode
(6) PORT A: R05
PA5~PA0, I/O Register
(7) PORT B: R06
PB7~PB0, I/O Register
(8) PORT C: R07
PC7~PC0, I/O Register
(9) PORT D: R08
PD7~PD0, I/O Register
(10) PORT E: R09
PE2~PE0, I/O Register
(11) PCHLAT: R0A
(12) INTS (Interrupt Status Register): R0B
Bit
0
1
2
3
Symbol
RBIF
INTF
TIF
RBIE
Function
PORT B change interrupt flag, Set when PB <7：4> inputs change
Set when INT interrupt occurs
Set when TMR0 overflows
0: Disable PB change interrupt
1: Enable PB change interrupt
4
INTS
0: Disable INT interrupt
1: Enable INT interrupt
5
TIS
0: Disable TMR0 interrupt
1: Enable TMR0 interrupt
6
PEIE
0: Disable all peripheral interrupt
1: Enable all peripheral interrupt
7
GIS
0: Disable global interrupt
1: Enable global interrupt
This specification are subject to be changed without notice. Any latest information
please preview http;//www.mdtic.com.tw
P. 6
2008/06 Ver. 1.2
MDTIC [ Micon Design Technology Corporation ]
