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MG87FE/L2051/4051/6051
Preliminary, v 1.03
5.2. CPU Timing
A machine cycle is the shortest timing period to achieve an instruction. In MG87FE/L2051/4051/6051, some
instructions need 1 machine cycle to achieve, but others need 2 or 4 machine cycles. A machine cycle takes 12
clock periods or 6 clock periods. For 12MHz system clock, it is 1us or 0.5us.
A machine cycle is consisted of six sequential states. The states are from S1 to S6. For each state, it is
partitioned into two phase – phase1 and phase2. Each phase is corresponding to 1 clock period. Execution of a
one-cycle instruction begins during S1 when the op-code is latched into the instruction register. A second fetch
appears during S4 of the same machine cycle. Execution is completed at the end of S6 of the machine cycle.
MOVX instruction is in-active in MG87FE/L2051/4051/6051 because there is no on-chip external RAM and no
external access bus. Write operation will have no effect. And read operation will always cause an un-excepted
operation.
5.3. CPU Addressing Mode
Direct Addressing (DIR)
In direct addressing the operand is specified by an 8-bit address field in the instruction. Only internal data RAM
and SFRs can be direct addressed.
Indirect Addressing (IND)
In indirect addressing the instruction specified a register which contains the address of the operand. Both internal
and external RAM can be indirectly addressed.
The address register for 8-bit addresses can be R0 or R1 of the selected bank, or the Stack Pointer.
The address register for 16-bit addresses can only be the 16-bit data pointer register – DPTR.
Register Instruction (REG)
The register banks, containing registers R0 through R7, can be accessed by certain instructions which carry a
3-bit register specification within the op-code of the instruction. Instructions that access the registers this way are
code efficient because this mode eliminates the need of an extra address byte. When such instruction is
executed, one of the eight registers in the selected bank is accessed.
Register-Specific Instruction
Some instructions are specific to a certain register. For example, some instructions always operate on the
accumulator or data pointer, etc. No address byte is needed for such instructions. The op-code itself does it.
Immediate Constant (IMM)
The value of a constant can follow the op-code in the program memory.
Index Addressing
Only program memory can be accessed with indexed addressing and it can only be read. This addressing mode
is intended for reading look-up tables in program memory. A 16-bit base register(either DPTR or PC) points to
the base of the table, and the accumulator is set up with the table entry number. Another type of indexed
addressing is used in the conditional jump instruction.
In conditional jump, the destination address is computed as the sum of the base pointer and the accumulator.
This document information is the intellectual property of Megawin Technology.
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Megawin Technology Co., Ltd. 2009 All rights reserved.
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