Megawin Technology Co., Ltd.
P3.0 (RXD)
P3.1 (TXD)
P3.2 (INT0)
P3.3 (INT1)
P3.4 (T0)
P3.5 (T1)
P3.6 (/WR)
P3.7 (/RD)
10
11
12
13
14
15
16
17
11
13
14
15
16
17
18
19
5
7
8
9
10
11
12
13
MG87FE/L52
I/O Port 3 is an 8-bit bidirectional I/O port
with internal pull-ups and can be used
as inputs. Port 3 pins that have 1s
written to them are pulled high by the
internal pull-ups and can be used as
inputs. As inputs, port 3 pins that are
externally pulled low will source current
because of the internal pull-ups. Port3
also serves other special functions of
this device.
P3.0 and P3.1 act as receiver and
transceiver of the data for UART
function block, Alias RXD and TXD.
P3.2 and P3.3 also act as external
interrupt sources, alias INT0 and INT1.
P3.4 and P3.5 also act as event
sources for timer0 and
individually, alias T0 and T1.
timer1
P3.6 also acts as write signal while
access to external memory, alias /WR.
P3.7 also acts as read signal while
access to external memory, alias /RD.
P4.0
P4.1
P4.2 (/INT3)
P4.3 (/INT2)
RESET
9
23
34
1
12
10
17
28
39
6
4
I
I/O Port4 is extended I/O ports such like
Port1. It can be available only on
44L-PLCC and 44L-PQFP package.
P4.2 and P4.3 also act as external
interrupt sources, alias INT3 and INT2.
A high on this pin for at least two
machine cycles will reset the device.
ALE
30
33
27
O
Output pulse for latching the low bytes
of address during accesses to external
memory.
/PSEN
29
32
26
O
The read strobe to external program
memory, low active.
/EA
31
35
29
I
/EA must be kept at low to enable the
device to fetch program code from
external flash memory.
An internal pull-up resistor has been
embedded in this pin.
XTAL1
XTAL2
19
18
21
20
15
14
I
O
Input to
amplifier.
the
inverting
oscillator
Output from the inverting amplifier.
Preliminary
ver 1.3
Date: 2009-JAN-20
5
MEGAWIN [ MEGAWIN TECHNOLOGY CO., LTD ]
