MG87FE/L2051/4051/6051
Preliminary, v 1.03
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Bit 7~0: The IAPLB determines the IAP-memory lower boundary. Since a Flash page has 512 bytes, the IAPLB
must be an even number.
To read IAPLB, MCU need to define the IMFT for mode selection on IAPLB Read and set ISPCR.ISPEN. And
then write 0x46h & 0xB9h sequentially into SCMD. The IAPLB content is available in IFD. If write IAPLB, MCU
will put new IAPLB setting value in IFD firstly. And then select IMFT, enable ISPCR.ISPEN and then set SCMD.
The IAPLB content has already finished the updated sequence.
The range of the IAP-memory is determined by IAPLB and the ISP start address as listed below.
IAP lower boundary = IAPLBx256, and
IAP higher boundary = ISP start address – 1.
For example, if IAPLB=0x12 and ISP start address is 0x1C00, then the IAP-memory range is located at 0x1200 ~
0x1BFF.
Additional attention point, the IAP low boundary address must not be higher than ISP start address.
SCMD: Sequential Command Data register / RDID (Read DID register)
Address=E6H, read/write, Power On + RESET=xxxx-xxxx
7
6
5
4
3
2
1
0
SCMD
SCMD is the command port for triggering ISP/IAP/IAPLB activity. If SCMD is filled with sequential 0x46h, 0xB9h
and if ISPCR.7 = 1, ISP/IAP activity will be triggered.
ISPCR: ISP Control Register
Address=E5H, read/write, Power On + RESET= 0000-xxxx
7
6
5
4
3
-
2
1
0
ISPEN
SWBS
SWRST
CFAIL
Bit 7: ISPEN, ISP/IAP operation enable.
0: Global disable all ISP/IAP program/erase/read function.
1: Enable ISP/IAP program/erase/read function.
Bit 6: SWBS, software boot selection control.
0: Boot from main-memory after reset.
1: Boot from ISP memory after reset.
Bit 5: SWRST, software reset trigger control.
0: No operation
1: Generate software system reset. It will be cleared by hardware automatically.
Bit 4: CFAIL, Command Fail indication for ISP/IAP operation.
0: The last ISP/IAP command has finished successfully.
1: The last ISP/IAP command fails. It could be caused since the access of flash memory was inhibited.
Bit 3~0 : Reserved.
MG87FE/L2051/4051/6051 does not make use of idle-mode to perform ISP operation. Instead, it creates CPU
wait-state to release flash memory for ISP control circuit use. Once ISP run over, CPU will be waken-up and
advanced to the instruction which follows the previous instruction that invokes ISP activity. During ISP operation,
interrupt service is also blocked until ISP run over.
ISP control circuit has a built-in timer for timing sequence control. It is referred from OSC frequency and defined
by CKCON2.XCKS[5:0] to get the accuracy erase/program timing.
This document information is the intellectual property of Megawin Technology.
© Megawin Technology Co., Ltd. 2009 All rights reserved.
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