System Control Registers
Power saving control
Address
Name
PWR_CTL
0200H
Write “0” to Bit 7
Bit 7
0
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
CKC
Bit 0
HALT
R
-
W
√
When the low-voltage detector is enabled, and it senses the power voltage is lower than V
LVR
, the
chip would be reset automatically.
CKC: Oscillator control bit. 1: disable OSC, 0: enable OSC
HALT: FCPU off-line control bit. 1: FCPU off-line, 0: FCPU on-line
Program can switch the normal operation mode to the power-saving mode for saving power
consumption through this register. There are two power saving mode in this system.
Stop mode: (PWR_CTL.CKC = 1)
System clock stops oscillating. The uC can be awakened from stop mode by 5 ways: port 3
interrupt, hardware reset, power-on reset, USB Host Reset and USB Host Resume.
Halt mode: (PWR_CTL.HALT = 1)
The FCPU clock in off-line status. The oscillator oscillates or not depends on the content of
PWR_CTL.CKC. The uC can be awakened from halt mode by 3-ways: interrupts (USB, Timer 0,
Port 3, Port0.4, Port0.5) assigned in the RLH_EN register, hardware reset, or power-on reset.
Release halt mode enable flag
Address
Name
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
0202H
RLH_EN
-
-
P05
P04
P3
TM0
USB
Program can select interrupt sources to release halt mode through this register.
0: Disable (default)
1: Enable
Release halt status flag is the IRQ_ST register.
Bit 0
-
R
-
W
√
14
MPC235 Data Sheet
MEGAWIN
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