The user must not clear the bit; otherwise, there could be inadvertent effect impacted on the
device.
OSCDN: =
Used to adjust the behavior of crystal oscillator.
0:=
The current gain of crystal oscillator amplifier is reduced. It will bring
help to EMI reducing and improve the power consumption. Dealing with application does
not need high frequency clock (under 12MHz). It is recommended to do so.
1:=
(default)
The current gain of crystal oscillator is enough for oscillator to start oscillating up to 24MHz.
HWBS2:=
Used to adjust the behavior of crystal oscillator.
0:=
Force the boot entrance as ISP code for both of power-up boot and RST-pin boot.
1:=
(default)
Transfer the determination of boot entrance to
HWBS.
By using HWBS2, ISP program may be triggered to run by RESET pin. (See Boot and
Reset section)
ENROSC: =
Used to determined if to enable the built-in RC oscillator.
0:=
Clearing the bit will enable the built-in RC oscillator, and set that oscillator as the oscillating
source
1:=
(default)
Setting the bit means to disable the built-in RC oscillator.
NVM register: OR3 (Option Register 3):
Bit-7
reserved1
Bit-6
reserved1
Bit-5
HWENW
Bit-4
-
Bit-3
HWWIDL
Bit-2
HWPS2
Bit-1
HWPS1
Bit-0
HWPS0
reserved1:=
The bit is reserved for afterward user, and should be left at set.
The user must not clear the bit; otherwise, there could be inadvertent effect impacted on the
device.
HWENW: =
Hardware Enable Watch-dog-timer
0:=
Clearing the bit will automatically enable the watch-dog-timer after power-up immediately.
HWWIDL, HWPS2, HWPS1
and
HWPS0
will be loaded Into SFR WDTCR after power-up if
and only if
HWENW =0.
1:=
(default)
No Hardware enable for Watch-dog-timer.
HWWIDL: =
Hardware enables reset from Watch-dog-timer in spite of the MCU lies idle.
0:=
Watch-dog-timer is also suspended while the MCU lies idle.
1:=
(default)
Enable watch-dog-timer to keep working in spite of the MCU has been put into idle mode.
If the bit
HWENW
is left
1,
the bits
HWWIDL, HWPS2, HWPS1 and HWPS0
make no sense.
{HWPS2, HWPS1, HWPS0}:=
Hardware Watch-dog-timer Pre-Scalar
If the bit
HWENW
is cleared to
0,
those bits will be loaded into SFR
WDTCR
after power-up.
Those three bits set the pre-scalar of the watch-dog-timer.
If the bit
HWENW
is left
1,
those three bits makes no sense.
{0,0,0}:=
The frequency of the clock source for the watch-dog-timer is divided by 2.
{0,0,1}:=
The frequency of the clock source for the watch-dog-timer is divided by 4.
18
MPC82x54A Data Sheet
MEGAWIN
MEGAWIN [ MEGAWIN TECHNOLOGY CO., LTD ]
