SFR:
TCON
(Timer/Counter Control Register)
Bit-7
TF1
Bit-6
TR1
Bit-5
TF0
Bit-4
TR0
Bit-3
IE1
Bit-2
IT1
Bit-1
IE0
Bit-0
IT0
TF1:
= Timer1 overflow flag.
This bit is automatically set by hardware on
T1
overflow, and will be automatically cleared by
hardware when the processor vectors to the interrupt routine.
TR1:
= Timer1 run control bit.
0:=
(default)
Stop
T1
counting
1:=
Start
T1
counting
TF0:
= Timer0 overflow flag.
This bit is automatically set by hardware on
T0
overflow, and will be automatically cleared by
hardware when the processor vectors to the interrupt routine.
TR0:
= Timer0 run control bit.
0:=
(default)
Stop
T0
counting
1:=
Start
T0
counting
IE1:
= External Interrupt-1 flag.
This bit is automatically set by hardware on interrupt from the external interrupt-1, and will be
automatically cleared by hardware when the processor vectors to the interrupt routine.
IT1:
= Interrupt-1 type control bit.
0:=
(default)
Set the interrupt-1 triggered by low duty from pin EX1
1:=
Set the interrupt-1 triggered by negative falling edge from pin EX1
IE0:
= External Interrupt-0 flag.
This bit is automatically set by hardware on interrupt from the external interrupt-0, and will be
automatically cleared by hardware when the processor vectors to the interrupt routine.
IT0:
= Interrupt-0 type control bit.
0:=
(default)
Set the interrupt-0 triggered by low duty from pin EX0
1:=
Set the interrupt-0 triggered by negative falling edge from pin EX0
MEGAWIN
MPC82x54A Data Sheet
25
MEGAWIN [ MEGAWIN TECHNOLOGY CO., LTD ]
