RAM
There are 512 bytes RAM built in MPC82x54A.
The user can visit the leading 128-byte RAM via direct addressing instructions, and we name
those RAM as direct RAM that occupies address space 00h to 7Fh.
Followed 128-byte RAM can be visited via indirect addressing instructions, and we name
those RAM as indirect RAM that occupied address space 80h to FFh.
There are extra 256 bytes RAM can be visited via MOVX @Ri or @DPTR instructions which
are named external RAM. When using MOVX @DPTR, the content in DPH is ignored. None
of P0 status and P2 status is affected during MOVX instruction.
Nonvolatile Registers:
There are four Nonvolatile Registers named OR0, OR1, OR2, and OR3 individually. They are
designed to configure the MPC82x54A, i.e.,: to decide to use internal RC oscillator or use
crystal oscillator as oscillating source, or to allocate the built-in flash for application program,
application data and In-System-Program code.
Generally, the only way to program those four nonvolatile registers is making use of a popular
NVM writer, such as: Hi-Lo System All-11, Leaper-48 and Megawin-Provided MCU writer. The
user’s program and the ISP program never can change those option registers.
NVM register: OR0 (Option Register 0):
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
LVFWP
ENLVR
ISPAS1
ISPAS0
HWBS
reserved1 SB
LOCK
LVFWP: = Low-Voltage-Flag-Write-Protecting bit.
0:=
inhibit the flash read/write action via ISP/IAP mechanism while the power supply drops
under a specific voltage level. Typically, the voltage threshold is around 3.7V/2.3V (Operate
in the 5V / 3V) for Fosc =12MHz.
1:= (default)
No inhibition on the flash-writing action.
ENLVR: =Enable-Low-Voltage-Reset
0:=
Clearing the bit will reset the device while the power supply drops under a specific voltage
level. Typically, the voltage threshold is around 3.7V/2.3V (Operate in the 5V / 3V) for
Fosc = 12MHz.
1:= (default)
Setting the bit implies never reset the device in spite of voltage dropping.
16
MPC82x54A Data Sheet
MEGAWIN
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