MPC82X52AE 参数 Datasheet PDF下载

Power Management

IDLE Mode

An instruction setting

PCON.0

causes the device go into the idle mode, and the internal clock

is gated off to the CPU but not to the interrupt, timer, PCA, SPI, ADC, WDT and serial port

functions.

There are two ways to terminate the idle. Activation of any enabled interrupt will cause

PCON.0

to be cleared by hardware in order to terminating the idle mode. The interrupt will be

serviced, and following RETI instruction: the next instruction to be executed will be performed

right after the instruction that puts the device into idle. Another way to wake-up from idle is to

pull pin RST high to generate internal hardware reset.

Save Power Consumption under IDLE Mode

A clock divider(CLKDIV) associated with idle mode is used to slow down the system clock

source in order to save power in advance. Slower the clock oscillates, and less power is

consumed. Software could program this clock divider register prior to enter the idle mode.

When the chip enters the idle mode, the clock is switched to the divider. When the chip exits

the idle mode, clocking will return to the original clock behavior.

SFR:

PCON2 (Power

Control 2)

Bit-7

-

Bit-6

-

Bit-5

-

Bit-4

-

Bit-3

-

Bit-2

CKS2

Bit-1

CKS1

Bit-0

CKS0

{CKS2, CKS1, CKS0 }:

Clock selector under idle mode

{0, 0,0}

: = (default)

In idle mode, clock is not divided (default state)

{0, 0, 1}

: =

In idle mode, clock is divided by 2

{0, 1, 0}

: =

In idle mode, clock is divided by 4

{0, 1, 1}

: =

In idle mode, clock is divided by 8

{1, 0,0}

: =

In idle mode, clock is divided by 16

{1, 0, 1}

: =

In idle mode, clock is divided by 32

{1, 1, 0}

: =

In idle mode, clock is divided by 64

{1, 1, 1}

: =

In idle mode, clock is divided by 128

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MPC82x52A Data Sheet

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