Mode 0
The timer register is configured as a 13-bit register. As the count rolls over from all 1s to all 0s,
it sets the timer interrupt flag
TFx.
The counted input is enabled to the timer when
TRx
= 1
and either GATE=0 or INTx = 1. Mode 0 operation is the same for Timer0 and Timer1.
OSC/12
OSC
AUXR.x
0
1
T0 or T1 pin
(sampled)
C//T
TRx
GATE
/INTx
0
1
0
1
TLx[4:0] THx[7:0]
TFx
Interrupt
Mode 1
Mode1 is the same as Mode0, except that the timer register is being run with all 16 bits.
OSC/12
OSC
AUXR.x
0
1
T0 or T1 pin
(sampled)
C//T
TRx
GATE
/INTx
0
1
0
1
TLx[7:0] THx[7:0]
TFx
Interrupt
Mode 2
Mode 2 configures the timer register as an 8-bit counter (TLx) with automatic reload. Overflow
from TLx does not only set TFx, but also reloads TLx with the content of THx, which is
determined by user’s program. The reload leaves THx unchanged. Mode 2 operation is the
same for Timer0 and Timer1.
OSC/12
OSC
AUXR.x
0
1
T0 or T1 pin
(sampled)
C//T
TRx
GATE
/INTx
THx [7:0]
0
1
Reload
0
1
TLx [7:0]
TFx
Interrupt
MEGAWIN
MPC82x54A Data Sheet
27
MEGAWIN [ MEGAWIN TECHNOLOGY CO., LTD ]
