interrupt. Neither of these flags is cleared by hardware when the service routine is vectored to.
The service routine should poll them to determine which one to request service and it will be
cleared by software.
All of the bits that generate interrupts can be set or cleared by software with the same result
as done through it by hardware. In other words, interrupts or pending interrupts can be
generated or canceled in software.
The following content describes several SFR related to interrupt mechanism.
SFR:
IE
(Interrupt Enable)
Bit-7
EA
Bit-6
Bit-5
Bit-4
ES
Bit-3
ET1
Bit-2
EX1
Bit-1
ET0
Bit-0
EX0
EPCA_LVD ESPI_ADC
EA:=Global
interrupt controller.
0:=(default)
Disable all interrupts
1:=
Release interrupt control to all individual interrupt controllers.
EPCA_LVD:=Interrupt
controller of Programmable Counter Array (PCA) and Low-Voltage
Detector
0:=(default)
Disable
1:=
Enable
ESPI_ADC:=
Interrupt controller of Serial Peripheral Interface (SPI) and A/D Converter (ADC).
0:=(default)
Disable
1:=
Enable
ES:=Interrupt
controller of Universal Asynchronous Receiver/Transmitter (UART).
0:=(default)
Disable
1:=
Enable
ET1:=Interrupt
controller of Timer-1 interrupt.
0:=(default)
Disable
1:=
Enable
EX1:=Interrupt
controller of external interrupt-1.
0:=(default)
Disable
1:=
Enable
30
MPC82x54A Data Sheet
MEGAWIN
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