IP (or XICON) and IPH are combined to form 4-level priority interrupt as the following table.
{IPH.x , IP.x}
11
10
01
00
Priority
Level
1 (highest)
2
3
4
SFR:
XICON
(External
Interrupt Control):
Bit-7
PX3
Bit-6
EX3
Bit-5
IE3
Bit-4
IT3
Bit-3
PX2
Bit-2
EX2
Bit-1
IE2
Bit-0
IT2
PX3
: If set, Set priority for external interrupt 3 higher
EX3
: If set, Enables external interrupt 3.
IE3
IT3
: Interrupt 3 Edge flag. Sets by hardware when external interrupt edge detected. Cleared when
interrupt processed.
: Interrupt 3 type control bit. Set/Cleared by software to specified falling edge/low level triggered
interrupt.
PX2
: If set, Set priority for external interrupt 3 higher
EX2
: If set, enables external interrupt 2.
IE2
IT2
: Interrupt 2 Edge flag. Sets by hardware when external interrupt edge detected. Cleared when
interrupt processed.
: Interrupt 2 types control bit. Set/Cleared by software to specify falling edge/low level triggered
interrupt.
Watchdog Timer
CLK/12
8
8-bit pre-scalar timer
15-bit WDT
RESET
ENW
IDLE
WIDL
PS0
PS1
PS2
CLRW
22
MPC89x53A Data Sheet
MEGAWIN