EVB71102
315/433MHz Receiver
Evaluation Board Description
1.3
Block Diagram
IN_MIX1
OUT_MIX2
FBC1
IF1N
VCC_MIX
VEE_LNAC
GAIN_LNA
OUT_LNA
VEE_MIX
OUT_IFA
IN_DEM
IF1P
VEE_IF
IN_IFA
2
3
4
5
6
7
8
9
RSSI
1
10
11
12
13
21
14
15
16
IN_LNA
31
MIX1
LNA
LO1
IF1
MIX2
IF2
LO2
MIX3
OUTP
OUTN
23
24
IFA
OAP
OA
DIV8
DIV2
PFD
RO
VCO1
VCC_LNA
VEE_LNA
20
OAN
19
OUT_OA
BIAS
VCC_BIAS
VEE_BIAS
VCC_PLL
VEE_RO
18
CP
ENRX
32
30
29
LF
26
RO
25
27
28
22
17
Fig. 1: TH71102 block diagram
1.4
Mode Configurations
ENRX
0
1
Mode
RX standby
RX active
Description
RX disabled
RX enable
Note:
ENRX are pulled down internally
1.5
LNA GAIN Control
V
GAIN_LNA
< 0.8 V
> 1.4 V
Mode
HIGH GAIN
LOW GAIN
Description
LNA set to high gain
LNA set to low gain
Note:
hysteresis between gain modes to ensure stability
1.6
Frequency Planning
Frequency planning is straightforward for single-conversion applications because there is only one IF that
can be chosen, and then the only possible choice is low-side or high-side injection of the LO signal (which is
now the one and only LO signal in the receiver).
The receiver’s double-conversion architecture requires careful frequency planning. Besides the desired RF
input signal, there are a number of spurious signals that may cause an undesired response at the output.
Among them are the image of the RF signal (that must be suppressed by the RF front-end filter), spurious
signals injected to the first IF (IF1) and their images which could be mixed down to the same second IF (IF2)
as the desired RF signal (they must be suppressed by the LC filter at IF1 and/or by low-crosstalk design).
39012 71102 01
Rev. 011
Page 4 of 14
EVB Description
June/07
MELEXIS [ Melexis Microelectronic Systems ]
