EVB71120
300 to 930MHz Receiver
Evaluation Board Description
1.3
Block Diagram
VCC
IFSEL
MODSEL
LNAO2
MIXO
MIXN
VEE
2
LNAO1
MIXP
VEE
9
10
11
12
14
17
100k
16
100k
DF2
13
RSSI
DF1
3
6
4
5
27
24
ASK
OA1
SW1
100k
100k
DFO
18
LNAI1
1
LNA1
MIX1
MIX2
IFA
FSK
LNASEL
32
PKDET+
20
LNAI2
8
LO1
LO2
LNA2
N1
counter
VCO
BIAS
ENRX
FSK
DEMOD
PFD
RO
SW2
PDP
VEE
7
100k
PKDET_
PDN
21
RFSEL
31
SEQ
N2
counter
TEST
26
LF
CP
ROI
DIV 8
SLCSEL
CLKO
VCC
SLC
OA2
NCF
DTAO
29
CINT
22
19
23
30
25
28
15
Fig. 1:
MLX71120 block diagram
The MLX71120 receiver IC consists of the following building blocks:
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•
•
•
•
•
•
•
•
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PLL synthesizer (PLL SYNTH) to generate the first and second local oscillator signals LO1 and LO2.
The PLL SYNTH consists of a fully integrated voltage-controlled oscillator (VCO), a distributed feedback
divider chain (N1, N2), a phase-frequency detector (PFD) a charge pump (CP), a loop filter (LF) and a
crystal-based reference oscillator (RO).
Two low-noise amplifiers (LNA) for high-sensitivity RF signal reception
First mixer (MIX1) for down-conversion of the RF signal to the first IF (intermediate frequency)
Second mixer (MIX2) with image rejection for down-conversion from the first to the second IF
IF amplifier (IFA) to provide a high voltage gain and an RSSI signal output
FSK demodulator (FSK DEMOD)
Operational amplifiers OA1 and OA2 for low-pass filtering and data slicing, respectively
Positive (PKDET+) and negative (PKDET-) peak detectors
Switches SW1 to select between FSK and ASK as well as SW2 to chose between averaging or peak
detection mode.
Noise cancellation filter (NF)
Sequencer circuit (SEQ) and biasing (BIAS) circuit
Clock output (DIV8)
Y
R
A
IN
IM
L
E
R
P
39012 71120 01
Rev. 003
Page 4 of 18
EVB Description
Jan/08
MELEXIS [ Melexis Microelectronic Systems ]
