EVB71122
300 to 930MHz Receiver
Evaluation Board Description
3.1.2
Control Word R1
Name
Bits
00
01
10
11
0
1
0
1
00
01
10
11
100µA
400µA
400µA static down
400µA static up
PFD output polarity
PFDPOL
[2]
negative
positive
lock detector time error
LDERR
[3]
15ns
30ns
lock detection time
2/f
R
4/f
R
8/f
R
16/f
R
minimum time span before lock in
f
R
is the reference oscillator frequency f
RO
divided by R, see section 4.1.5 (R4)
Description
charge pump current setting
#default
CPCUR
[1:0]
#default
#default
LDTIME
[5:4]
#default
LDMODE
[6]
VCORANGE
[7]
VCOCUR
[8]
VCOBUF
[9]
Y
R
A
IN
IM
L
E
R
P
lock detector mode
0
1
0
1
check lock condition permanently
check lock condition until 1
st
lock in
VCO range
3V supply
5V supply
VCO range setting for different VCCs.
#default
#default
VCO core current
0
1
0
1
0
1
450µA
520µA
#default
VCO buffer current
900µA
1040µA
20µA
30µA
#default
prescaler 32/33 reference current
PRESCUR
[10]
#default
30µA may be used for f
RF
= 868/915MHz
function of LDRSSIL bit
SHOWLD
[11]
0
1
RSSIL (RSSI low flag)
LD (lock detection flag)
select output data of LDRSSIL, see section 4.1.8 (R7)
#default
39012 71122 01
Rev. 001
Page 16 of 32
EVB Description
Sept/06
MELEXIS [ Melexis Microelectronic Systems ]
