EVB71122
300 to 930MHz Receiver
Evaluation Board Description
1.3
Block Diagram
LNAO
VEELNA
VCCANA
RSSI
3
4
8
9
MODSEL
DF2
2
VEEIF
6
MIXP
5
MIXN
DF1
1
28
200k
29
200k
ASK
OA1
DFO
27
MIX1
LNAI
31
200k
1M
LNA
LO1
IF1
MIX2
IF2
IFF
IFA
FSK
SW1
PKDET+
25
LO2
FSK
DEMOD
1M
PDP
LO2DIV
N/A
counter
VCO
LF
VCCVCO
VEEVCO
MFO
PKDET_
PDN
26
PFD
R
counter
Control
Logic
C/SDEN
B/SDTA
SPISEL
A/SCLK
SLCSEL
SW2
CP
RO
BIAS
VEEANA
VCCDIG
VEEDIG
OA2
DTAO
22
SLC
RBIAS
32
11
14
TNK1
12 13
TNK2
15
23
24
7
17
18
19
10
16
ENRX
ROI
LF
20
21
30
Fig. 1:
MLX71122 block diagram
The MLX71122 receiver IC consists of the following building blocks:
•
•
•
•
•
•
•
•
•
•
•
•
PLL synthesizer (PLL SYNTH) to generate the first and second local oscillator signals LO1 and LO2,
parts of the PLL SYNTH are the voltage-controlled oscillator (VCO), the feedback dividers N/A and R,
the phase-frequency detector (PFD), the charge pump (CP) and the crystal-based reference oscillator
(RO)
Low-noise amplifier (LNA) for high-sensitivity RF signal reception
First mixer (MIX1) for down-conversion of the RF signal to the first IF (intermediate frequency)
Second mixer (MIX2) with image rejection for down-conversion from the first to the second IF
IF Filter (IFF) with a 2MHz center frequency and a 230kHz 3dB bandwidth
IF amplifier (IFA) to provide a large amount of voltage gain and an RSSI signal output
FSK demodulator (FSK DEMOD)
Operational amplifiers OA1 and OA2 for low-pass filtering and data slicing, respectively
Positive (PKDET+) and negative (PKDET-) peak detectors
Switches SW1 to select between FSK and ASK as well as SW2 to chose between averaging or peak
detector data slicer
Control logic with 3-wire bus serial programming interface (SPI)
Biasing circuit with modes control
Y
R
A
IN
IM
L
E
R
P
For more detailed information, please refer to the latest MLX71122 data sheet revision.
39012 71122 01
Rev. 001
Page 5 of 32
EVB Description
Sept/06
MELEXIS [ Melexis Microelectronic Systems ]
