EVB7122
27 to 930MHz Transceiver
Evaluation Board Description
3.1.3
B – word
Name
Bits
[9:0]
4d .. 1023d
Set the desired steady state current of the reference oscillator
000
001
010
011
100
101
110
111
0
μA
75
μA
150
μA
#default
225
μA
300
μA
375
μA
450
μA
525
μA
0
μA
75
μA
150
μA
225
μA
300
μA
375
μA
450
μA
525
μA
#default
disabled
enabled
OA2 can be enabled in FSK receive mode. OA2 is disabled in ASK mode receive.
The control circuitry regulates the current of the oscillator core
between the values ROMAX and ROMIN. As the regulation input
signal the amplitude on pin RO is used. If the ROMIN value is
sufficient to achieve an amplitude of about 400mV on pin RO the
current of the reference oscillator core will be set to ROMIN.
Otherwise the current will be permanently regulated between
ROMAX and ROMIN. If ROMIN and ROMAX are equal no
regulation of the oscillator current occurs. Please also note the
block description of the reference oscillator in para. 3.1.1
Description
Reference divider ratio in TX operation mode
RT
ROMIN
[12:10]
Set the start-up current of the reference oscillator
000
001
010
011
100
101
110
111
ROMAX
[15:13]
Set the start-up current of the reference oscillator core. Please
also note the description of the ROMIN register and the block
description of the reference oscillator which can be seen above.
OA2 operation
OA2
[16]
0
1
#default
Internal AFC feature
AFC
[17]
0
1
disabled
enabled
Hysteresis on pin GAIN_LNA
#default
LNAHYST
[18]
0
1
0
disabled
enabled
- typical 340 mV (V
0→1
= 1.56V, V
1→0
= 1.22V)
Delayed start of the PLL
undelayed start
PLL starts at the reference oscillator start-up
#default
DELPLL
[19]
1
starts after 8 valid RO-cycles
#default
PLL starts after 8 valid RO-cycles before entering an active mode to ensure reliable oscillation
of the reference oscillator.
not used
[20]
0
disabled
set to ‘1’ for correct function
RSSI Peak Detector
#default
PKDET
[21]
1
The RSSI output signal directly feeds the data slicer setup by means of OA1.
enabled
In ASK receive mode the RSSI Peak Detector output is multiplexed to pin INT2/PDO.
39012 07122 02
Rev. 005
Page 10 of 24
EVB Description
June/07
MELEXIS [ Melexis Microelectronic Systems ]
